公开(公告)号：US20050171937A1

公开(公告)日：2005-08-04

申请号：US10769941

申请日：2004-02-02

申请人： Martin Hughes ,  William Lee ,  Trevor Garner ,  Dennis Briddell

发明人： Martin Hughes ,  William Lee ,  Trevor Garner ,  Dennis Briddell

IPC分类号： G06F17/30

CPC分类号： G06F16/9014

摘要： A technique efficiently searches a hash table. Conventionally, a predetermined set of “signature” information is hashed to generate a hash-table index which, in turn, is associated with a corresponding linked list accessible through the hash table. The indexed list is sequentially searched, beginning with the first list entry, until a “matching” list entry is located containing the signature information. For long list lengths, this conventional approach may search a substantially large number of list entries. In contrast, the inventive technique reduces, on average, the number of list entries that are searched to locate the matching list entry. To that end, list entries are partitioned into different groups within each linked list. Thus, by searching only a selected group (e.g., subset) of entries in the indexed list, the technique consumes fewer resources, such as processor bandwidth and processing time, than previous implementations.

摘要翻译： 一种技术有效地搜索哈希表。 常规地，预定的一组“签名”信息被散列以产生哈希表索引，该哈希表索引又与通过散列表可访问的对应链表相关联。 依次搜索索引列表，从第一个列表条目开始，直到包含签名信息的“匹配”列表条目为止。 对于长列表长度，这种常规方法可以搜索大量的列表条目。 相比之下，本发明技术平均减少了搜索以定位匹配列表条目的列表条目的数量。 为此，列表条目在每个链接列表中被分成不同的组。 因此，通过仅搜索索引列表中的选择的组（例​​如，子集）条目，该技术比先前的实现消耗更少的资源，例如处理器带宽和处理时间。

公开(公告)号：US20080005296A1

公开(公告)日：2008-01-03

申请号：US11430116

申请日：2006-05-08

申请人： William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

发明人： William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

IPC分类号： G06F15/173

CPC分类号： H04L47/20 ,  H04L49/901 ,  H04L67/28

摘要： Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

摘要翻译： 用于同步数据的使用的技术，例如通过网络发送的分组，包括接收指示由DMA控制器拥有的特定缓冲器描述符的专用索引数据，用于在数据端口和对应的存储器缓冲器之间移动数据。 写命令被放置在存储器交换队列上，以将所有者更改为不同的处理器，并且私有索引数据被递增。 确定公共索引，其指示所有者最近更改为处理器并且已知对于处理器可见的不同缓冲器描述符。 响应于从处理器接收到更改为处理器所有权的最新缓冲器描述符的请求，将公共索引数据发送到处理器。 基于公共索引数据，处理器与保证由处理器拥有的缓冲区描述符交换数据。

公开(公告)号：US07461180B2

公开(公告)日：2008-12-02

申请号：US11430116

申请日：2006-05-08

申请人： William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

发明人： William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

IPC分类号： G05F13/00 ,  G06F15/173

CPC分类号： H04L47/20 ,  H04L49/901 ,  H04L67/28

摘要： Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

摘要翻译： 用于同步数据的使用的技术，例如通过网络发送的分组，包括接收指示由DMA控制器拥有的特定缓冲器描述符的专用索引数据，用于在数据端口和对应的存储器缓冲器之间移动数据。 写命令被放置在存储器交换队列上，以将所有者更改为不同的处理器，并且私有索引数据被递增。 确定公共索引，其指示所有者最近更改为处理器并且已知对于处理器可见的不同缓冲器描述符。 响应于从处理器接收到更改为处理器所有权的最新缓冲器描述符的请求，将公共索引数据发送到处理器。 基于公共索引数据，处理器与保证由处理器拥有的缓冲区描述符交换数据。

公开(公告)号：US20080013532A1

公开(公告)日：2008-01-17

申请号：US11484791

申请日：2006-07-11

申请人： Trevor Garner ,  William Lee ,  Hanli Zhang ,  Martin Hughes

发明人： Trevor Garner ,  William Lee ,  Hanli Zhang ,  Martin Hughes

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L45/302 ,  H04L45/38 ,  H04L45/60 ,  H04L47/10 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/34 ,  H04L49/90 ,  H04L49/901

摘要： An apparatus for routing data packets includes a network interface, a memory, a general purpose processor and a flow classifier. The memory stores a flow structure. Every packet in one flow has identical values for a set of data fields in the packet. The memory stores instruction that cause the processor to receive missing flow data and to add the missing flow to the flow structure. The apparatus forwards a packet based on the flow. The flow classifier determines a particular flow and whether it is already stored in the flow structure. If not, then the classifier determines whether that flow has already been sent to the processor as missing data. If not, then the classifier stores into a different data structure data that indicates the flow has been sent to the processor but is not yet included in the flow data structure, and sends missing data to the processor.

摘要翻译： 用于路由数据分组的装置包括网络接口，存储器，通用处理器和流分类器。 存储器存储流程结构。 一个流中的每个数据包对于数据包中的一组数据字段具有相同的值。 存储器存储使得处理器接收丢失的流数据并将丢失的流添加到流结构的指令。 该装置基于流转发分组。 流分类器确定特定的流程以及它是否已经存储在流结构中。 如果没有，则分类器确定该流是否已经作为丢失数据发送到处理器。 如果不是，则分类器将不同的数据结构存储在指示流已经发送到处理器但尚未包括在流数据结构中的数据中，并将丢失的数据发送到处理器。

公开(公告)号：US08228908B2

公开(公告)日：2012-07-24

申请号：US11484791

申请日：2006-07-11

申请人： Trevor Garner ,  William Lee ,  Hanli Zhang ,  Martin Hughes

发明人： Trevor Garner ,  William Lee ,  Hanli Zhang ,  Martin Hughes

IPC分类号： H04L12/28

CPC分类号： H04L45/00 ,  H04L45/302 ,  H04L45/38 ,  H04L45/60 ,  H04L47/10 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/34 ,  H04L49/90 ,  H04L49/901

摘要： An apparatus for routing data packets includes a network interface, a memory, a general purpose processor and a flow classifier. The memory stores a flow structure. Every packet in one flow has identical values for a set of data fields in the packet. The memory stores instruction that cause the processor to receive missing flow data and to add the missing flow to the flow structure. The apparatus forwards a packet based on the flow. The flow classifier determines a particular flow and whether it is already stored in the flow structure. If not, then the classifier determines whether that flow has already been sent to the processor as missing data. If not, then the classifier stores into a different data structure data that indicates the flow has been sent to the processor but is not yet included in the flow data structure, and sends missing data to the processor.

摘要翻译： 用于路由数据分组的装置包括网络接口，存储器，通用处理器和流分类器。 存储器存储流程结构。 一个流中的每个数据包对于数据包中的一组数据字段具有相同的值。 存储器存储使得处理器接收丢失的流数据并将丢失的流添加到流结构的指令。 该装置基于流转发分组。 流分类器确定特定的流程以及它是否已经存储在流结构中。 如果没有，则分类器确定该流是否已经作为丢失数据发送到处理器。 如果不是，则分类器将不同的数据结构存储在指示流已经发送到处理器但尚未包括在流数据结构中的数据中，并将丢失的数据发送到处理器。

公开(公告)号：US20050213570A1

公开(公告)日：2005-09-29

申请号：US10811195

申请日：2004-03-26

申请人： John Stacy ,  Trevor Garner ,  Martin Hughes ,  William Lee

发明人： John Stacy ,  Trevor Garner ,  Martin Hughes ,  William Lee

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L49/901 ,  H04L47/32 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9047 ,  H04L63/1416 ,  H04L63/1458

摘要： A system and method is provided for automatically identifying and removing malicious data packets, such as denial-of-service (DoS) packets, in an intermediate network node before the packets can be forwarded to a central processing unit (CPU) in the node. The CPU's processing bandwidth is therefore not consumed identifying and removing the malicious packets from the system memory. As such, processing of the malicious packets is essentially “off-loaded” from the CPU, thereby enabling the CPU to process non-malicious packets in a more efficient manner. Unlike prior implementations, the invention identifies malicious packets having complex encapsulations that can not be identified using traditional techniques, such as ternary content addressable memories (TCAM) or lookup tables.

摘要翻译： 提供了一种系统和方法，用于在分组可以转发到节点中的中央处理单元（CPU）之前自动识别和去除中间网络节点中的恶意数据分组，例如拒绝服务（DoS）分组。 因此，CPU的处理带宽不被识别并从系统内存中删除恶意数据包。 因此，恶意数据包的处理本质上从CPU中“卸载”，从而使CPU能够以更有效的方式处理非恶意数据包。 与先前的实现不同，本发明识别具有复杂封装的恶意数据包，这些封装不能使用诸如三进制内容可寻址存储器（TCAM）或查找表之类的传统技术来识别。

公开(公告)号：US07464243B2

公开(公告)日：2008-12-09

申请号：US11018368

申请日：2004-12-21

申请人： Sriram Haridas ,  Martin Hughes ,  William Lee ,  John Mitten

发明人： Sriram Haridas ,  Martin Hughes ,  William Lee ,  John Mitten

IPC分类号： G06F12/00

CPC分类号： G11C7/20

摘要： Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in memory. The length data indicates an amount of memory to be initialized. The pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data. The memory controller performs multiple write operations on memory beginning at a first location based on the address data and ending at a second location based on the length data. Each write operation writes the pattern data to a current location in memory, thereby initializing the arbitrary portion of memory with an arbitrary pattern based on the pattern data.

摘要翻译： 用于以任意模式初始化任意部分存储器的技术包括使用存储器控制器来执行顺序读取和写入操作。 存储器控制器在连接到处理器的数据总线上接收地址数据，长度数据和模式数据。 地址数据表示存储器中的位置。 长度数据表示要初始化的内存量。 模式数据指示比由长度数据指示的存储器的量短得多的特定的比特序列。 存储器控制器基于地址数据在第一位置开始对存储器执行多个写入操作，并且基于长度数据在第二位置结束。 每个写入操作将模式数据写入存储器中的当前位置，从而基于模式数据以任意模式初始化存储器的任意部分。

公开(公告)号：US20110064081A1

公开(公告)日：2011-03-17

申请号：US12947535

申请日：2010-11-16

申请人： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

发明人： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

IPC分类号： H04L12/56

CPC分类号： H04L45/60 ,  H04L45/00 ,  H04L49/602

摘要： Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

摘要翻译： 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中，确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存，用于确定类型。 此外，基于分类，处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题，从而节省高速缓存的多余的加载和弹出。

公开(公告)号：US07848332B2

公开(公告)日：2010-12-07

申请号：US10988754

申请日：2004-11-15

申请人： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

发明人： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

IPC分类号： H04L12/56

CPC分类号： H04L45/60 ,  H04L45/00 ,  H04L49/602

摘要： Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

摘要翻译： 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中，确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存，用于确定类型。 此外，基于分类，处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题，从而节省高速缓存的多余的加载和弹出。

公开(公告)号：US20060136682A1

公开(公告)日：2006-06-22

申请号：US11018368

申请日：2004-12-21

申请人： Sriram Haridas ,  Martin Hughes ,  William Lee ,  John Mitten

发明人： Sriram Haridas ,  Martin Hughes ,  William Lee ,  John Mitten

IPC分类号： G06F13/00

CPC分类号： G11C7/20

摘要： Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in memory. The length data indicates an amount of memory to be initialized. The pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data. The memory controller performs multiple write operations on memory beginning at a first location based on the address data and ending at a second location based on the length data. Each write operation writes the pattern data to a current location in memory, thereby initializing the arbitrary portion of memory with an arbitrary pattern based on the pattern data.

摘要翻译： 用于以任意模式初始化任意部分存储器的技术包括使用存储器控制器来执行顺序读取和写入操作。 存储器控制器在连接到处理器的数据总线上接收地址数据，长度数据和模式数据。 地址数据表示存储器中的位置。 长度数据表示要初始化的内存量。 模式数据指示比由长度数据指示的存储器的量短得多的特定的比特序列。 存储器控制器基于地址数据在第一位置开始对存储器执行多个写入操作，并且基于长度数据在第二位置结束。 每个写入操作将模式数据写入存储器中的当前位置，从而基于模式数据以任意模式初始化存储器的任意部分。