-
公开(公告)号：US08340240B2
公开(公告)日：2012-12-25
申请号：US13492916
申请日：2012-06-10
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。
-
公开(公告)号：US08229058B2
公开(公告)日：2012-07-24
申请号：US12607042
申请日：2009-10-27
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
-
公开(公告)号：US20120250816A1
公开(公告)日：2012-10-04
申请号：US13492916
申请日：2012-06-10
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。
-
公开(公告)号：US20100260312A1
公开(公告)日：2010-10-14
申请号：US12607042
申请日：2009-10-27
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。
-
公开(公告)号：US07817771B2
公开(公告)日：2010-10-19
申请号：US12334874
申请日：2008-12-15
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。
-
公开(公告)号：US08031827B2
公开(公告)日：2011-10-04
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。
-
公开(公告)号：US20110007863A1
公开(公告)日：2011-01-13
申请号：US12877748
申请日：2010-09-08
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。
-
公开(公告)号：US20110158376A1
公开(公告)日：2011-06-30
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/34
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
-
公开(公告)号：US07924967B2
公开(公告)日：2011-04-12
申请号：US12877748
申请日：2010-09-08
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
-
公开(公告)号：US20080088559A1
公开(公告)日：2008-04-17
申请号：US11882349
申请日：2007-08-01
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3655 , G09G2300/0447 , G09G2320/0204 , G09G2320/0257 , G09G2320/028 , G09G2320/0673
摘要： Disclosed is a method for driving a display panel. The display panel includes a plurality of unit pixels and a plurality of switches. The switches are used for controlling the unit pixels to display. The method includes transmitting a plurality of gate signals to the switches for driving the switches. More, the driving method also includes transmitting a plurality of data signals to the switches for providing a plurality of pixel voltages to the unit pixels and providing common voltages to the unit pixels as well as generating the potential differences with the common voltage and the pixel voltages of the unit pixels for controlling the display of the unit pixels by a group time. The total amount of potential differences in each unit pixel in the group time is substantially equal to zero. The group time includes a plurality of driving unit times. In each driving unit time, at least one group of pixels displays. A group of pixels includes a plurality of grayscale levels of brightness. The total brightness of the grayscale levels accords with a predetermined brightness. Therefore, the display not only can increase its viewing angel, but also can avoid residual image caused from residual charge.
摘要翻译： 公开了一种用于驱动显示面板的方法。 显示面板包括多个单位像素和多个开关。 开关用于控制显示的单位像素。 该方法包括将多个门信号发送到用于驱动开关的开关。 此外，驱动方法还包括向开关发送多个数据信号，以向单位像素提供多个像素电压并向单位像素提供公共电压，以及产生与公共电压和像素电压的电位差 的单位像素，用于按组时间控制单位像素的显示。 组合时间中每个单位像素的电位差的总量基本上等于零。 组时间包括多个驱动单元次数。 在每个驱动单元中，显示至少一组像素。 一组像素包括多个灰度等级的亮度。 灰度级的总亮度与预定亮度一致。 因此，显示器不仅可以增加其观看角度，而且可以避免残留电荷引起的残留图像。
-
-
-
-
-
-
-
-
-
搜索结果
77 条记录 (耗时 0.042 秒)
