公开(公告)号：US08031827B2

公开(公告)日：2011-10-04

申请号：US13041794

申请日：2011-03-07

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。

公开(公告)号：US20110007863A1

公开(公告)日：2011-01-13

申请号：US12877748

申请日：2010-09-08

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。

公开(公告)号：US20110158376A1

公开(公告)日：2011-06-30

申请号：US13041794

申请日：2011-03-07

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

IPC分类号： G11C19/34

CPC分类号： G11C19/28

摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

公开(公告)号：US07924967B2

公开(公告)日：2011-04-12

申请号：US12877748

申请日：2010-09-08

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

公开(公告)号：US07817771B2

公开(公告)日：2010-10-19

申请号：US12334874

申请日：2008-12-15

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Po-Yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。

公开(公告)号：US20100260312A1

公开(公告)日：2010-10-14

申请号：US12607042

申请日：2009-10-27

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

公开(公告)号：US20120250816A1

公开(公告)日：2012-10-04

申请号：US13492916

申请日：2012-06-10

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

公开(公告)号：US08340240B2

公开(公告)日：2012-12-25

申请号：US13492916

申请日：2012-06-10

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

公开(公告)号：US08229058B2

公开(公告)日：2012-07-24

申请号：US12607042

申请日：2009-10-27

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

公开(公告)号：US08049828B2

公开(公告)日：2011-11-01

申请号：US12178662

申请日：2008-07-24

申请人： Chun-Hsin Liu ,  Yung-Chih Chen ,  Po-Yuan Liu ,  Tsung-Ting Tsai

发明人： Chun-Hsin Liu ,  Yung-Chih Chen ,  Po-Yuan Liu ,  Tsung-Ting Tsai

IPC分类号： G02F1/1333 ,  G02F1/1345

CPC分类号： G02F1/1362 ,  G02F1/13454 ,  G02F1/136286 ,  G02F2001/136254 ,  G02F2203/69

摘要： A flat-panel display device having test architecture is disclosed for disposing shorting bars without sacrificing wiring-on-array bus layout area of the outer-lead-bonding region. The flat-panel display device essentially includes a substrate having a plurality of driving integrated-circuit (IC) mounting areas, a plurality of signal lines and transmission lines disposed on the substrate, and a plurality of shorting bars disposed on the driving IC mounting areas. Each shorting bar is coupled to a corresponding signal line and a corresponding transmission line. Furthermore, in order to take out the laser-cutting process in the fabrication of the flat-panel display device for saving production cost, each driving IC mounting area is further disposed with a plurality of transistors for controlling the signal connections between the shorting bars and the signal lines, and also for controlling the signal connections between the shorting bars and the transmission lines.

摘要翻译： 公开了一种具有测试架构的平板显示装置，用于在不牺牲外引线接合区域的阵列总线布局面积的情况下设置短路棒。 平板显示装置基本上包括具有多个驱动集成电路（IC）安装区域的基板，设置在基板上的多条信号线和传输线以及设置在驱动IC安装区域上的多个短路棒 。 每个短路条耦合到对应的信号线和对应的传输线。 此外，为了在制造平板显示装置的同时取出激光切割工艺以节省生产成本，每个驱动IC安装区域还配置有多个晶体管，用于控制短路棒和短路棒之间的信号连接 信号线，并且还用于控制短路棒和传输线之间的信号连接。