公开(公告)号：US20100150303A1

公开(公告)日：2010-06-17

申请号：US12502696

申请日：2009-07-14

申请人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Min-feng Chiang ,  Po-yuan Liu

发明人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Min-feng Chiang ,  Po-yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2330/025

摘要： A shift register includes a plurality of shift register stages cascade-connected with each other. Each shift register stage includes a pull up module for outputting an output pulse in response to a first clock signal, a pull-up driving module for turning on the pull up module in response to a driving pulse of a previous one stage of the shift register, a pre-pull-down module coupled to a previous two stage of the shift register and a first node for pulling down voltage level of the first node in response to a output pulse of the previous two stage of the shift register, a pull down module coupled to the first node for pulling down voltage level of the first node in response to a pulling-down triggering signal, and a pulling down driving module for providing the pulling-down triggering signal.

摘要翻译： 移位寄存器包括彼此级联的多个移位寄存器级。 每个移位寄存器级包括用于响应于第一时钟信号输出输出脉冲的上拉模块，用于响应于移位寄存器的前一级的驱动脉冲导通上拉模块的上拉驱动模块 耦合到移位寄存器的前两级的预下拉模块和用于响应于移位寄存器的前两级的输出脉冲而拉低第一节点的电压电平的第一节点，下拉 耦合到第一节点的模块，用于响应于下拉触发信号而降低第一节点的电压电平，以及用于提供下拉触发信号的下拉驱动模块。

公开(公告)号：US07953201B2

公开(公告)日：2011-05-31

申请号：US12502696

申请日：2009-07-14

申请人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Min-feng Chiang ,  Po-yuan Liu

发明人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Min-feng Chiang ,  Po-yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2330/025

摘要： A shift register includes a plurality of shift register stages cascade-connected with each other. Each shift register stage includes a pull up module for outputting an output pulse in response to a first clock signal, a pull-up driving module for turning on the pull up module in response to a driving pulse of a previous one stage of the shift register, a pre-pull-down module coupled to a previous two stage of the shift register and a first node for pulling down voltage level of the first node in response to a output pulse of the previous two stage of the shift register, a pull down module coupled to the first node for pulling down voltage level of the first node in response to a pulling-down triggering signal, and a pulling down driving module for providing the pulling-down triggering signal.

摘要翻译： 移位寄存器包括彼此级联的多个移位寄存器级。 每个移位寄存器级包括用于响应于第一时钟信号输出输出脉冲的上拉模块，用于响应于移位寄存器的前一级的驱动脉冲导通上拉模块的上拉驱动模块 耦合到移位寄存器的前两级的预下拉模块和用于响应于移位寄存器的前两级的输出脉冲而拉低第一节点的电压电平的第一节点，下拉 耦合到第一节点的模块，用于响应于下拉触发信号而降低第一节点的电压电平，以及用于提供下拉触发信号的下拉驱动模块。

公开(公告)号：US20090304138A1

公开(公告)日：2009-12-10

申请号：US12409280

申请日：2009-03-23

申请人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

发明人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit.

摘要翻译： 本文介绍了一种用于减小时钟耦合效应的移位寄存器和移位寄存器单元。 每级移位寄存器单元包括至少一个上拉驱动模块，上拉模块，至少一个下拉模块和下拉驱动模块。 在由上拉模块采用的第一时钟信号或第二时钟信号的波形进入上升沿之前，下拉驱动模块采用第一周期信号来预先为下拉模块接通 在上拉模块采用的第一或第二时钟信号的波形转入下降沿之前和/或之前，下拉驱动模块采用第二周期信号预先关闭下拉模块 在一段特定的时期。 因此，下拉模块可以针对时钟耦合效应获得足够的能力，以优化从移位寄存器单元输出的波形。

公开(公告)号：US07688934B2

公开(公告)日：2010-03-30

申请号：US12409280

申请日：2009-03-23

申请人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

发明人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit.

摘要翻译： 本文介绍了一种用于减小时钟耦合效应的移位寄存器和移位寄存器单元。 每级移位寄存器单元包括至少一个上拉驱动模块，上拉模块，至少一个下拉模块和下拉驱动模块。 在由上拉模块采用的第一时钟信号或第二时钟信号的波形进入上升沿之前，下拉驱动模块采用第一周期信号来预先为下拉模块接通 在上拉模块采用的第一或第二时钟信号的波形转入下降沿之前和/或之前，下拉驱动模块采用第二周期信号预先关闭下拉模块 在一段特定的时期。 因此，下拉模块可以针对时钟耦合效应获得足够的能力，以优化从移位寄存器单元输出的波形。

公开(公告)号：US07949086B2

公开(公告)日：2011-05-24

申请号：US12480020

申请日：2009-06-08

申请人： Tsung-ting Tsai ,  Yung-chih Chen

发明人： Tsung-ting Tsai ,  Yung-chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.

摘要翻译： 移位寄存器包括彼此级联的多个寄存器单元。 每个寄存器单元包括上拉电路，上拉驱动电路，下拉电路和下拉驱动电路。 耦合到第一时钟信号的上拉电路用于提供输出信号。 上拉驱动电路响应于来自先前寄存器单元和第二时钟信号的驱动脉冲而导通，并响应于第三时钟信号而截止。 耦合到下拉电路的输入节点的下拉驱动电路响应于第一时钟信号而导通，并响应于第一时钟信号或上拉驱动电路的输出而断开 。

公开(公告)号：US08175215B2

公开(公告)日：2012-05-08

申请号：US12572247

申请日：2009-10-01

申请人： Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

发明人： Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.

摘要翻译： 移位寄存器包括多个级联连接级。 每一级响应于时钟信号和第一控制信号产生输出信号。 每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。 上拉模块用于根据时钟信号提供输出信号。 上拉驱动模块响应于第一控制信号而导通上拉模块。 第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。 第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。 第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

公开(公告)号：US20100226473A1

公开(公告)日：2010-09-09

申请号：US12572247

申请日：2009-10-01

申请人： Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

发明人： Chun-Hsin Liu ,  Tsung-ting Tsai ,  Kuo-Chang Su ,  Yung-Chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.

摘要翻译： 移位寄存器包括多个级联连接级。 每一级响应于时钟信号和第一控制信号产生输出信号。 每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。 上拉模块用于根据时钟信号提供输出信号。 上拉驱动模块响应于第一控制信号而导通上拉模块。 第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。 第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。 第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

公开(公告)号：US20090304139A1

公开(公告)日：2009-12-10

申请号：US12480020

申请日：2009-06-08

申请人： Tsung-ting Tsai ,  Yung-chih Chen

发明人： Tsung-ting Tsai ,  Yung-chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.

摘要翻译： 移位寄存器包括彼此级联的多个寄存器单元。 每个寄存器单元包括一个上拉电路，一个上拉驱动电路，一个下拉电路和一个下拉驱动电路。 耦合到第一时钟信号的上拉电路用于提供输出信号。 上拉驱动电路响应于来自先前寄存器单元和第二时钟信号的驱动脉冲而导通，并响应于第三时钟信号而截止。 耦合到下拉电路的输入节点的下拉驱动电路响应于第一时钟信号而导通，并且响应于第一时钟信号或上拉驱动电路的输出而断开 。