公开(公告)号：US20100255802A1

公开(公告)日：2010-10-07

申请号：US12417512

申请日：2009-04-02

申请人： Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

发明人： Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

IPC分类号： H04B1/16

CPC分类号： H04B1/3805 ,  H04B15/06

摘要： An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

摘要翻译： 具有宽频率范围的FM收音机在手机中工作，而不会干扰RF收发器的VCO。 FM收发器产生一个VCO信号，其频率从窄的第一范围的中点变化小于±7％。 通过将VCO频率除以第一因子来产生合成器信号，使得合成器频率在较低频率的第二范围内变化。 VCO频率也被第二除数除以使得合成器频率在第三范围内变化。 第二范围的上限落在第三范围的下限。 第二范围的下限为85.5MHz，第三范围的上限为108.0MHz。 通过使用第三除数，从窄的第一频率范围产生具有76-108MHz范围的合成器信号。

公开(公告)号：US08254849B2

公开(公告)日：2012-08-28

申请号：US12417512

申请日：2009-04-02

申请人： Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

发明人： Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

IPC分类号： H04B1/06

CPC分类号： H04B1/3805 ,  H04B15/06

摘要： An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

摘要翻译： 具有宽频率范围的FM收音机在手机中工作，而不会干扰RF收发器的VCO。 FM收发器产生一个VCO信号，其频率从窄的第一范围的中点变化小于±7％。 通过将VCO频率除以第一因子来产生合成器信号，使得合成器频率在较低频率的第二范围内变化。 VCO频率也被第二除数除以使得合成器频率在第三范围内变化。 第二范围的上限落在第三范围的下限。 第二范围的下限为85.5MHz，第三范围的上限为108.0MHz。 通过使用第三除数，从窄的第一频率范围产生具有76-108MHz范围的合成器信号。

公开(公告)号：US08437721B2

公开(公告)日：2013-05-07

申请号：US12430106

申请日：2009-04-26

申请人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

发明人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H04B1/1027

摘要： A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

摘要翻译： FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。 如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。 如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。 通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。 通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。

公开(公告)号：US20100273442A1

公开(公告)日：2010-10-28

申请号：US12430106

申请日：2009-04-26

申请人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

发明人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

IPC分类号： H04B1/16

CPC分类号： H04B1/1027

摘要： A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

摘要翻译： FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。 如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。 如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。 通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。 通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。

公开(公告)号：US20100330941A1

公开(公告)日：2010-12-30

申请号：US12492407

申请日：2009-06-26

申请人： Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

发明人： Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

IPC分类号： H04B1/18

CPC分类号： H04H20/57 ,  H04H40/45

摘要： A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

摘要翻译： 描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。 补偿单元可以补偿PLL的闭环响应的调制信号。 缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

公开(公告)号：US08169270B2

公开(公告)日：2012-05-01

申请号：US12437462

申请日：2009-05-07

申请人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

发明人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293

摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

摘要翻译： VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。 粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。 微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。 为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值 精细电容器组的调谐电容器元件是有效的。

公开(公告)号：US08688045B2

公开(公告)日：2014-04-01

申请号：US12274167

申请日：2008-11-19

申请人： I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

发明人： I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

IPC分类号： H04B1/00

CPC分类号： H04B1/525

摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

摘要翻译： 示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。 数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。 低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。 放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。 数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

公开(公告)号：US08442466B2

公开(公告)日：2013-05-14

申请号：US12492407

申请日：2009-06-26

申请人： Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

发明人： Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H04H20/57 ,  H04H40/45

摘要： A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

摘要翻译： 描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。 补偿单元可以补偿PLL的闭环响应的调制信号。 缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

公开(公告)号：US20100124891A1

公开(公告)日：2010-05-20

申请号：US12274167

申请日：2008-11-19

申请人： I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

发明人： I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

IPC分类号： H03D5/00

CPC分类号： H04B1/525

摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

摘要翻译： 示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。 数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。 低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。 放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。 数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

公开(公告)号：US20100283551A1

公开(公告)日：2010-11-11

申请号：US12437462

申请日：2009-05-07

申请人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

发明人： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293

摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

摘要翻译： VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。 粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。 微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。 为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值 精细电容器组的调谐电容器元件是有效的。