公开(公告)号：US08437721B2

公开(公告)日：2013-05-07

申请号：US12430106

申请日：2009-04-26

Applicant: Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

Inventor： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

IPC: H04B1/06 ,  H04B7/00

CPC classification number: H04B1/1027

Abstract: A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

Abstract translation: FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。 如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。 如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。 通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。 通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。

公开(公告)号：US20100156532A1

公开(公告)日：2010-06-24

申请号：US12340142

申请日：2008-12-19

Applicant: Cheng-Han Wang ,  Tzu-wang Pan ,  Roger Brockenbrough

Inventor： Cheng-Han Wang ,  Tzu-wang Pan ,  Roger Brockenbrough

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F1/307

Abstract: A class AB amplifier with resistive level-shifting circuitry is described. In one exemplary design, the class AB amplifier includes an input stage, a resistive level-shifting stage, a class AB output stage, and a bias circuit. The input stage receives an input signal and provides a first drive signal. The resistive level-shifting stage receives the first drive signal and provides a second drive signal. The output stage receives the first and second drive signals and provides an output signal. The bias circuit generates a bias voltage for the resistive level-shifting stage to obtain a desired quiescent current for the output stage. In one exemplary design, the resistive level-shifting stage includes a transistor and a resistor. The transistor receives the bias voltage and provides the second drive signal. The resistor is coupled to the transistor and provides a voltage drop between the first and second drive signals.

Abstract translation: 描述了具有阻性电平移位电路的AB类放大器。 在一个示例性设计中，AB类放大器包括输入级，电阻电平转换级，AB类输出级和偏置电路。 输入级接收输入信号并提供第一驱动信号。 电阻电平转换级接收第一驱动信号并提供第二驱动信号。 输出级接收第一和第二驱动信号并提供输出信号。 偏置电路产生用于电阻电平移位级的偏置电压，以获得用于输出级的期望的静态电流。 在一个示例性设计中，电阻电平移位级包括晶体管和电阻器。 晶体管接收偏置电压并提供第二驱动信号。 电阻器耦合到晶体管并且在第一和第二驱动信号之间提供电压降。

公开(公告)号：US06798301B1

公开(公告)日：2004-09-28

申请号：US09879824

申请日：2001-06-11

Applicant: Vishnu Balan ,  Tzu-Wang Pan

Inventor： Vishnu Balan ,  Tzu-Wang Pan

IPC: H03B100

CPC classification number: H03J3/20 ,  H03B5/366 ,  H03J2200/10

Abstract: A circuit controls an oscillation amplitude of a crystal oscillator including a crystal resonator, a current source supplying a bias current, and an output transistor coupled to the crystal resonator and the current source. The circuit includes a peak detector for detecting a peak voltage of an output signal of the crystal oscillator, and a controller coupled to the peak detector and to the current source for controlling the current source in accordance with a difference between the peak voltage and a target voltage, the target voltage being set to be substantially equal to 2Vth, where Vth is a threshold voltage of the output transistor. A frequency control circuit controls a first switched-capacitor array and a second switched-capacitor array coupled to the crystal resonator, and alternately switches a unit capacitor in the first switched-capacitor array and a unit capacitor in the second switched-capacitor array based on a frequency control signal.

Abstract translation: 电路控制包括晶体谐振器，提供偏置电流的电流源和耦合到晶体谐振器和电流源的输出晶体管的晶体振荡器的振荡幅度。 该电路包括用于检测晶体振荡器的输出信号的峰值电压的峰值检测器，以及耦合到峰值检测器和电流源的控制器，用于根据峰值电压和目标值之间的差来控制电流源 电压，目标电压被设定为基本上等于2Vth，其中Vth是输出晶体管的阈值电压。 频率控制电路控制耦合到晶体谐振器的第一开关电容器阵列和第二开关电容器阵列，并且交替地切换第一开关电容器阵列中的单位电容器和第二开关电容器阵列中的单位电容器，基于 频率控制信号。

公开(公告)号：US5644595A

公开(公告)日：1997-07-01

申请号：US456654

申请日：1995-06-02

Applicant: Richard G. Yamasaki ,  Tzu-Wang Pan

Inventor： Richard G. Yamasaki ,  Tzu-Wang Pan

IPC: H03H21/00 ,  G11B20/10 ,  H03H15/00 ,  H03H17/00 ,  H03M13/23 ,  H03M13/39 ,  H04B3/04 ,  H03H7/30 ,  G11B5/035

CPC classification number: G11B20/10009

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm. In systems employing separate adaptive loops for gain control, timing recovery and equalization, the amount of undesired loop interaction is much reduced from that of prior art methods.

Abstract translation: 一种用于部分响应信号的改进的自适应三抽头横向均衡器。 本发明降低了硬件的复杂性，同时降低了均衡器对增益和定时误差的敏感性。 本发明采用基于零附近的样本值的算法。 由此导致的误差的平均幅度的降低导致对增益误差的敏感性降低。 本发明的算法改进了采样定时误差的消除。 在本发明中，通过随机梯度的积分来更新自适应余弦均衡器的系数。 为了计算梯度，将来自先前样本的量化输出和当前样本的输出的乘积与来自先前样本的输出和当前样本的量化输出的乘积相加。 另外，均衡器输出被屏蔽，使得量化到非零值的值在更新算法中被丢弃。 在采用单独的自适应环路用于增益控制，定时恢复和均衡的系统中，与现有技术方法相比，不期望的环路相互作用量大大降低。

公开(公告)号：US5311178A

公开(公告)日：1994-05-10

申请号：US930718

申请日：1992-08-14

Applicant: Tzu-Wang Pan ,  Richard G. Yamasaki

Inventor： Tzu-Wang Pan ,  Richard G. Yamasaki

IPC: G11B20/10 ,  G11B20/14 ,  H03L7/06 ,  H04L7/033 ,  G11B5/09

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/1403 ,  H04L7/0334

Abstract: The present invention describes an improved RLL channel utilizing a closed-loop clock recovery scheme and a simplified decoding algorithm. (1,7) run-length-limited (RLL) code is used to reduce the magnetic nonlinearity problem posed by prior art PRML systems. In the preferred embodiment of the present invention, the analog data signal amplified, filtered and equalized to approximate an ideal waveform. The signal is then sampled and decoded into binary data. The clock recovery circuit is designed to sample the analog data such that the signal peak lies centered between consecutive sample points. It is thus made possible for the phase error to be extracted from a direct comparison of neighboring sample values. The phase error is then used to adjust the clock signal for the following samples. In the decoding algorithm of the present invention, by making useful approximations, the complexity of the decision functions is reduced, along with the number of required look-ahead samples. The reduction in look-ahead samples reduces the system's sensitivity to misequalization.

Abstract translation: 本发明描述了利用闭环时钟恢复方案和简化的解码算法的改进的RLL信道。 （1,7）游程限制（RLL）代码用于减少由现有技术的PRML系统构成的磁性非线性问题。 在本发明的优选实施例中，模拟数据信号被放大，滤波和均衡以接近理想波形。 然后将信号采样并解码成二进制数据。 时钟恢复电路被设计为对模拟数据进行采样，使得信号峰位于连续采样点之间的中心。 因此，可以从相邻采样值的直接比较中提取相位误差。 然后，相位误差用于调整以下样本的时钟信号。 在本发明的解码算法中，通过进行有用的近似，减少了决定函数的复杂度以及所需要的先行样本的数量。 预测样本的减少降低了系统对门槛资格的敏感性。

公开(公告)号：US08295798B2

公开(公告)日：2012-10-23

申请号：US12254129

申请日：2008-10-20

Applicant: Cheng-Han Wang ,  Roger Brockenbrough ,  Tzu-wang Pan

Inventor： Cheng-Han Wang ,  Roger Brockenbrough ,  Tzu-wang Pan

IPC: H04B1/06

CPC classification number: H03H11/1291

Abstract: An apparatus includes first and second filters and a bandwidth control circuit. The first filter operates as part of a first oscillator in a first mode and filters a first input signal and provides a first output signal in a second mode. The second filter operates as part of a second oscillator in the first mode and filters a second input signal and provides a second output signal in the second mode. The bandwidth control circuit adjusts the bandwidth of the first and second filters in the first mode, e.g., adjusts the oscillation frequency of each oscillator to obtain a target bandwidth for an associated filter. The apparatus may further include first and second gain control circuits. Each gain control circuit may vary the amplitude of an oscillator signal from an associated oscillator and/or set a gain of an associated filter in the first mode.

Abstract translation: 一种装置包括第一和第二滤波器以及带宽控制电路。 第一滤波器在第一模式中作为第一振荡器的一部分进行操作，并且对第一输入信号进行滤波并在第二模式中提供第一输出信号。 第二滤波器在第一模式中作为第二振荡器的一部分进行操作，并且对第二输入信号进行滤波并在第二模式中提供第二输出信号。 带宽控制电路在第一模式中调整第一和第二滤波器的带宽，例如调整每个振荡器的振荡频率以获得相关滤波器的目标带宽。 该装置还可以包括第一和第二增益控制电路。 每个增益控制电路可以改变来自相关振荡器的振荡器信号的幅度和/或在第一模式中设置相关联的滤波器的增益。

公开(公告)号：US08143941B2

公开(公告)日：2012-03-27

申请号：US12617428

申请日：2009-11-12

Applicant: Sunghyun Park ,  Xiaoyong Li ,  Tzu-wang Pan

Inventor： Sunghyun Park ,  Xiaoyong Li ,  Tzu-wang Pan

IPC: H03K5/00

CPC classification number: H03H11/126

Abstract: An active analog filter (700, 1000) having a MOS capacitor device (730, 1030) with improved linearity is proposed. In an exemplary embodiment, dc bias voltage sources (755, 745) alter the capacitance of MOS varactors (740, 750) connected in anti parallel so that the total capacitance of the MOS capacitor device remains constant or within a range over the voltage range of the filter and the filter linearity is set. In a further exemplary embodiment the output stage (1070) of the operational amplifier circuit (1020) of the active analog filter (1000) is modified so that the dc bias voltage is provided by resistors (1055, 1045) connected to a current source (1060) already existing in the filter. Thus the linearity is set and the die area is significantly reduced.

Abstract translation: 提出了一种具有提高线性度的MOS电容器件（730,1030）的有源模拟滤波器（700,1000）。 在示例性实施例中，直流偏置电压源（755,745）改变以反并联方式连接的MOS可变电抗器（740,750）的电容，使得MOS电容器装置的总电容保持恒定或超过电压范围 滤波器和滤波器线性度被设置。 在另一示例性实施例中，有源模拟滤波器（1000）的运算放大器电路（1020）的输出级（1070）被修改，使得直流偏置电压由连接到电流源的电阻（1055,1045） 1060）已经存在于过滤器中。 因此，设置线性度并且模具面积显着减小。

公开(公告)号：US20100283551A1

公开(公告)日：2010-11-11

申请号：US12437462

申请日：2009-05-07

Applicant: Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

Inventor： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293

Abstract: A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

Abstract translation: VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。 粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。 微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。 为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值 精细电容器组的调谐电容器元件是有效的。

公开(公告)号：US20100255802A1

公开(公告)日：2010-10-07

申请号：US12417512

申请日：2009-04-02

Applicant: Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

Inventor： Tzu-wang Pan ,  Yi Zeng ,  I-Hsiang Lin ,  Pushp K. Trikha ,  Jeremy D. Dunworth ,  Rahul Apte

IPC: H04B1/16

CPC classification number: H04B1/3805 ,  H04B15/06

Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

Abstract translation: 具有宽频率范围的FM收音机在手机中工作，而不会干扰RF收发器的VCO。 FM收发器产生一个VCO信号，其频率从窄的第一范围的中点变化小于±7％。 通过将VCO频率除以第一因子来产生合成器信号，使得合成器频率在较低频率的第二范围内变化。 VCO频率也被第二除数除以使得合成器频率在第三范围内变化。 第二范围的上限落在第三范围的下限。 第二范围的下限为85.5MHz，第三范围的上限为108.0MHz。 通过使用第三除数，从窄的第一频率范围产生具有76-108MHz范围的合成器信号。

公开(公告)号：US20100099372A1

公开(公告)日：2010-04-22

申请号：US12254129

申请日：2008-10-20

Applicant: Cheng-Han Wang ,  Roger Brockenbrough ,  Tzu-wang Pan

Inventor： Cheng-Han Wang ,  Roger Brockenbrough ,  Tzu-wang Pan

IPC: H04B1/16 ,  H03H7/00

CPC classification number: H03H11/1291

Abstract: An apparatus includes first and second filters and a bandwidth control circuit. The first filter operates as part of a first oscillator in a first mode and filters a first input signal and provides a first output signal in a second mode. The second filter operates as part of a second oscillator in the first mode and filters a second input signal and provides a second output signal in the second mode. The bandwidth control circuit adjusts the bandwidth of the first and second filters in the first mode, e.g., adjusts the oscillation frequency of each oscillator to obtain a target bandwidth for an associated filter. The apparatus may further include first and second gain control circuits. Each gain control circuit may vary the amplitude of an oscillator signal from an associated oscillator and/or set a gain of an associated filter in the first mode.

Abstract translation: 一种装置包括第一和第二滤波器以及带宽控制电路。 第一滤波器在第一模式中作为第一振荡器的一部分进行操作，并且对第一输入信号进行滤波并在第二模式中提供第一输出信号。 第二滤波器在第一模式中作为第二振荡器的一部分进行操作，并且对第二输入信号进行滤波并在第二模式中提供第二输出信号。 带宽控制电路在第一模式中调整第一和第二滤波器的带宽，例如调整每个振荡器的振荡频率以获得相关滤波器的目标带宽。 该装置还可以包括第一和第二增益控制电路。 每个增益控制电路可以改变来自相关振荡器的振荡器信号的幅度和/或在第一模式中设置相关联的滤波器的增益。