公开(公告)号：US20160061528A1

公开(公告)日：2016-03-03

申请号：US14833774

申请日：2015-08-24

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Michael A. Derenge

IPC: F27D1/02 ,  H01L21/324

CPC classification number: H01L21/3245 ,  C30B35/00 ,  F27B17/0025 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02667 ,  H01L21/26546

Abstract: An improved methodology for annealing group III-nitride semiconductor device structures using novel weighted cover systems that protect an annealing cap during the semiconductor annealing process is disclosed. The weighted cover system is configured for preventing the escape of nitrogen from the capped semiconductor during annealing. In one particular embodiment, the weighted cover system comprises a protective cover configured to be placed on the capped semiconductor during the anneal, and one or more weights configured to be placed on the protective cover to provide sufficient downward force to the protective cover that is placed on the capped semiconductor.

Abstract translation: 公开了一种改进的使用在半导体退火过程中保护退火盖的新型加权覆盖系统III族氮化物半导体器件结构退火的方法。 加权覆盖系统被配置为防止在退火期间氮气从封盖半导体逸出。 在一个具体实施例中，加权覆盖系统包括被配置为在退火期间放置在封盖半导体上的保护盖，以及配置成放置在保护盖上的一个或多个重物，以向放置的保护盖提供足够的向下的力 在半导体封装上。

公开(公告)号：US10460955B2

公开(公告)日：2019-10-29

申请号：US14833774

申请日：2015-08-24

Applicant: U.S. Army Research Laboratory ATTN: RDRL-LOC-I

Inventor： Michael A. Derenge

IPC: H01L21/32 ,  H01L21/324 ,  C30B35/00

Abstract: An improved methodology for annealing group III-nitride semiconductor device structures using novel weighted cover systems that protect an annealing cap during the semiconductor annealing process is disclosed. The weighted cover system is configured for preventing the escape of nitrogen from the capped semiconductor during annealing. In one particular embodiment, the weighted cover system comprises a protective cover configured to be placed on the capped semiconductor during the anneal, and one or more weights configured to be placed on the protective cover to provide sufficient downward force to the protective cover that is placed on the capped semiconductor.