公开(公告)号：US12009390B2

公开(公告)日：2024-06-11

申请号：US17709383

申请日：2022-03-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Katsunori Ueno

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L21/04 ,  H01L21/265 ,  H01L21/324

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L21/046 ,  H01L21/26546 ,  H01L21/3245

摘要： A vertical MOSFET having a compound semiconductor layer is provided, the vertical MOSFET comprising a gate electrode, a gate insulating film provided between the gate electrode and the compound semiconductor layer, a drift region provided directly in contact with at least a part of the gate insulating film and being a part of the compound semiconductor layer, and a high resistance region provided at least in the drift region, is positioned below at least a part of the gate insulating film, and has a higher resistance value per unit length than that of the drift region.

公开(公告)号：US20230326764A1

公开(公告)日：2023-10-12

申请号：US18295656

申请日：2023-04-04

申请人： Tokyo Electron Limited

发明人： Robert D. Clark ,  Steven Consiglio

IPC分类号： H01L21/324 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213

CPC分类号： H01L21/3245 ,  H01L21/02175 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/32134

摘要： A method of forming a device includes providing a substrate containing an exposed semiconductor region, forming a metal oxide film over the exposed semiconductor region, and forming an oxygen-scavenging metal film over the metal oxide film. The method includes chemically reducing the metal oxide film to an elemental metal film by scavenging oxygen from the metal oxide film into the oxygen-scavenging metal film; and reacting the elemental metal film with the semiconductor region to form a metal-semiconductor layer, the metal-semiconductor layer forming a source/drain contact region of a transistor.

公开(公告)号：US20180330982A1

公开(公告)日：2018-11-15

申请号：US15774454

申请日：2016-11-10

申请人： Nanyang Technological University ,  Massachusetts Institute of Technology

发明人： Kwang Hong Lee ,  Chuan Seng Tan ,  Eugene A. Fitzgerald ,  Shuyu Bao ,  Eng Kian Kenneth Lee ,  David Kohen

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L23/00

CPC分类号： H01L21/76251 ,  H01L21/02002 ,  H01L21/02054 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/3245 ,  H01L21/762 ,  H01L21/8258 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L28/00 ,  H01L2224/27452 ,  H01L2224/29186 ,  H01L2224/83002 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83019 ,  H01L2224/8389 ,  H01L2924/10253 ,  H01L2924/10329

摘要： A method of manufacturing a hybrid substrate is disclosed, which comprises: bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the layer of dielectric material and second semiconductor substrate; removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and annealing the third combined substrate at a temperature about 250° C. to 1000° C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.

公开(公告)号：US09960043B2

公开(公告)日：2018-05-01

申请号：US15352811

申请日：2016-11-16

申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

发明人： Yasuyo Kurachi

IPC分类号： H01L21/265 ,  H01L21/311 ,  H01L21/78 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L23/544

CPC分类号： H01L21/2654 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/31116 ,  H01L21/3245 ,  H01L21/78 ,  H01L23/544 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2223/5446

摘要： A process of forming a semiconductor device using plasma processes is disclosed. The semiconductor device includes a device area, a scribed area, and a peripheral area on a wafer, where these areas have respective conductive regions. The process includes steps of (a) implanting ions to isolate the conductive regions in the device area from the conductive region in the scribed area; (b) forming a metal film so as to cover a back surface, a side, and the peripheral area in the top surface of the wafer; (c) deposing insulating film on a whole surface of the wafer; and (d) selectively etching, by the plasma process, the insulating film so as to expose the conductive regions in the device area and the scribed area. During the plasma process, the metal film in the back surface of the wafer is connected the apparatus ground that effectively dissipates charges induced by the plasm to the apparatus ground through the metal film.

公开(公告)号：US20180090452A1

公开(公告)日：2018-03-29

申请号：US15697261

申请日：2017-09-06

申请人： TOYODA GOSEI CO.. LTD.

发明人： Takahiro Fujii ,  Masayoshi Kosaki ,  Takaki NIWA

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/267 ,  H01L21/266 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L23/562 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/66666

摘要： There is provided a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises: forming at least part of a cap layer that is mainly composed of a nitride, on a semiconductor layer that is mainly composed of a group III nitride semiconductor; implanting a p-type impurity into the semiconductor layer with at least part of the cap layer formed thereon, by ion implantation; forming a block layer having a larger coefficient of thermal expansion than a coefficient of thermal expansion of the cap layer, as a surface layer on the cap layer; and heating the semiconductor layer with the block layer as the surface layer, to activate the p-type impurity.

公开(公告)号：US09837486B2

公开(公告)日：2017-12-05

申请号：US14854125

申请日：2015-09-15

申请人： Comptek Solutions Oy

发明人： Pekka Laukkanen ,  Jouko Lang ,  Marko Punkkinen ,  Marjukka Tuominen ,  Veikko Tuominen ,  Johnny Dahl ,  Juhani Vayrynen

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L29/02 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L21/324 ,  H01L29/201

CPC分类号： H01L29/02 ,  H01L21/02046 ,  H01L21/02109 ,  H01L21/02172 ,  H01L21/02241 ,  H01L21/28264 ,  H01L21/31666 ,  H01L21/3245 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205

摘要： A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET.

公开(公告)号：US09809452B2

公开(公告)日：2017-11-07

申请号：US15442952

申请日：2017-02-27

申请人： THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE

发明人： Babak Nikoobakht, IV

IPC分类号： B82B3/00 ,  B82B1/00 ,  H01L21/306 ,  H01L21/324 ,  H01L21/02 ,  B01L3/00

CPC分类号： B82B3/0019 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0896 ,  B81B2203/033 ,  B81C1/00063 ,  B81C2201/0149 ,  B82B1/001 ,  H01L21/02241 ,  H01L21/30612 ,  H01L21/3245

摘要： A process for making a nanoduct includes: disposing an etchant catalyst on a semiconductor substrate including a single crystal structure; heating the semiconductor substrate to an etching temperature; introducing an oxidant; contacting the semiconductor substrate with the oxidant in a presence of the etchant catalyst; anisotropically etching the semiconductor substrate by the etchant catalyst in a presence of the oxidant in an etch direction that is coincident along a crystallographic axis of the semiconductor substrate; and forming the nanoduct as the etchant catalyst propagates along a surface of the semiconductor substrate during anisotropically etching the semiconductor substrate, the nanoduct being crystallographically aligned with the crystallographic axis of the semiconductor substrate.

公开(公告)号：US20170278952A1

公开(公告)日：2017-09-28

申请号：US15460069

申请日：2017-03-15

申请人： TOYODA GOSEI CO.,LTD.

发明人： Tohru OKA ,  Nariaki TANAKA

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/207 ,  H01L21/265 ,  H01L21/225 ,  H01L29/20 ,  H01L21/266 ,  H01L29/10

CPC分类号： H01L29/66734 ,  H01L21/2258 ,  H01L21/26546 ,  H01L21/26553 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/7809 ,  H01L29/7813

摘要： A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

公开(公告)号：US20170278950A1

公开(公告)日：2017-09-28

申请号：US15456269

申请日：2017-03-10

申请人： Toyoda Gosei Co., Ltd.

发明人： Nariaki Tanaka ,  Tohru Oka

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/285 ,  H01L29/423 ,  H01L21/02 ,  H01L21/324 ,  H01L29/20 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/26553 ,  H01L21/28587 ,  H01L21/3245 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66522 ,  H01L29/7813 ,  H01L29/7827

摘要： A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm−2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm−2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which the p-type impurity contained in the p-type semiconductor layer is diffused is formed in at least part of the n-type semiconductor layer that is located below the n-type semiconductor region.

公开(公告)号：US20170253479A1

公开(公告)日：2017-09-07

申请号：US15442952

申请日：2017-02-27

申请人： GOVERNMENT OF THE USA, AS REPRESENT BY THE SECRETARY OF COMMERCE

发明人： BABAK NIKOOBAKHT, IV

IPC分类号： B82B3/00 ,  B01L3/00 ,  H01L21/324 ,  H01L21/02 ,  B82B1/00 ,  H01L21/306

CPC分类号： B82B3/0019 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0896 ,  B81B2203/033 ,  B81C1/00063 ,  B81C2201/0149 ,  B82B1/001 ,  H01L21/02241 ,  H01L21/30612 ,  H01L21/3245

摘要： A process for making a nanoduct includes: disposing an etchant catalyst on a semiconductor substrate including a single crystal structure; heating the semiconductor substrate to an etching temperature; introducing an oxidant; contacting the semiconductor substrate with the oxidant in a presence of the etchant catalyst; anisotropically etching the semiconductor substrate by the etchant catalyst in a presence of the oxidant in an etch direction that is coincident along a crystallographic axis of the semiconductor substrate; and forming the nanoduct as the etchant catalyst propagates along a surface of the semiconductor substrate during anisotropically etching the semiconductor substrate, the nanoduct being crystallographically aligned with the crystallographic axis of the semiconductor substrate.