公开(公告)号：US20030168694A1

公开(公告)日：2003-09-11

申请号：US10390946

申请日：2003-03-18

Applicant: U.S. PHILIPS CORPORATION

Inventor： Roy Arthur Colclaser ,  Guido Jozef Maria Dormans ,  Donald Robert Wolters

IPC: H01L029/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25); the at least one memory cell having a floating gate (5), a tunnel oxide layer (11) between the floating gate and the substrate (1), a control gate (15), and a control oxide layer (13) between the control gate (15) and the floating gate (5); the at least one logic transistor (25) having a logic transistor gate (5null, 15null) and a logic transistor gate oxide (11null) between the logic transistor gate (5null, 15null) and the substrate (1), the tunnel oxide layer (11) of the memory cell (3) and the logic transistor gate oxide (11null) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor (17) which is optionally made so as to be an integral part of at least the memory cell (3).

Abstract translation: 具有在单个衬底（1）至少一个存储单元（3）和至少一个逻辑晶体管（25）上的半导体器件; 所述至少一个存储单元具有浮置栅极（5），在所述浮置栅极和所述衬底（1）之间的隧道氧化物层（11），控制栅极（15）和所述控制栅极 门（15）和浮动门（5）; 所述至少一个逻辑晶体管（25）具有逻辑晶体管栅极（5'，15“）和逻辑晶体管栅极（5'，15”）之间的逻辑晶体管栅极氧化物（11“）和衬底 1），存储单元（3）的隧道氧化物层（11）和逻辑晶体管栅极氧化物（11“）具有相同或基本相同的预定第一厚度。 本发明还涉及一种制造这种器件的方法以及这种器件，其还包括高压晶体管（17），其可选地制成为至少是存储器单元（3）的整体部分。