公开(公告)号：US20030191999A1

公开(公告)日：2003-10-09

申请号：US10407088

申请日：2003-04-04

Applicant: U.S. PHILIPS CORPORATION

Inventor： Richard Petrus Kleihorst ,  Renatus Josephus Van Der Vleuten ,  Nico Frits Benschop ,  Geeke Muurling

IPC: G06F011/00 ,  G01R031/28

CPC classification number: G06F11/085 ,  H03M13/00

Abstract: Errors are corrected that occur in the operation of a combinatorial logic circuit in an integrated circuit. The combinatorial circuit computes a vector of intermediate signals from the input signal. The combinatorial logic circuit is designed so that, when the combinatorial logic circuit operates without error, the vector belongs to an error correcting code, not being a repetition code. The combinatorial logic circuit comprises combinatorial logic sections, each for computing a respective one of the intermediate signals independently from the other sections. An error correction circuit computes an output signal from the vector, with a computation that maps erroneous vectors to the output signal for a nearest correct vector from the error correcting code when these erroneous vectors differ from the correct vector in less than a predetermined number of the intermediate signals.

公开(公告)号：US20010041012A1

公开(公告)日：2001-11-15

申请号：US09878677

申请日：2001-06-11

Applicant: U.S. PHILIPS CORPORATION.

Inventor： Jeff Hsieh ,  Richard Petrus Kleihorst ,  Andre Van Der Avoird

IPC: H04N007/12 ,  G06K009/36 ,  G06K009/46

CPC classification number: G06F7/762 ,  G06F7/76 ,  H04N5/335

Abstract: The invention provides a parallel data processing device having an array of parallel processing elements (LPA1 . . . 320) for processing a signal to obtain parallel streams of data, and means (TSMM1 . . . 80) for shuffling the parallel streams of data in a block-wise manner. The data shuffling means (TSMM1 . . . 80) have an array of addressable switch memory matrices (TSMM1 . . . 80) which are each coupled to a predetermined number of processing elements (LPA1 . . . 320). The array of switch memory matrices (TSMM1 . . . 80) solves data flow limitations of highly parallel linear array processors as well as intermediate storage requirements of image processing algorithms. In a camera system the parallel data processing device is combined with a sensor array (S).

Abstract translation: 本发明提供了一种并行数据处理设备，其具有用于处理信号以获得并行数据流的并行处理元件阵列（LPA1 ... 320），以及用于混合数据并行流的装置（TSMM1,80 ...） 一个块状的方式。 数据混洗装置（TSMM1 ... 80）具有可寻址的开关存储器矩阵（TSMM1 ... 80）的阵列，它们各自耦合到预定数量的处理元件（LPA1 ... 320）。 开关存储器矩阵（TSMM1 ... 80）阵列解决了高度并行的线性阵列处理器的数据流限制以及图像处理算法的中间存储要求。 在相机系统中，并行数据处理装置与传感器阵列（S）组合。