公开(公告)号：US20190013324A1

公开(公告)日：2019-01-10

申请号：US15641560

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

公开(公告)号：US10177165B1

公开(公告)日：2019-01-08

申请号：US15641560

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28 ,  H01L29/51

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.