公开(公告)号：US20190027589A1

公开(公告)日：2019-01-24

申请号：US15655881

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/465

CPC classification number: H01L29/66969 ,  H01L21/465 ,  H01L29/7869

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

公开(公告)号：US20190109199A1

公开(公告)日：2019-04-11

申请号：US15725288

申请日：2017-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Shao-Hui Wu ,  Xiang Li ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/49 ,  H01L21/225 ,  H01L21/02 ,  H01L29/786 ,  H01L29/04

Abstract: An oxide semiconductor device includes an oxide semiconductor channel layer, a first gate dielectric layer, a first gate electrode, a source electrode, and a drain electrode. The oxide semiconductor channel layer includes a channel region. The first gate dielectric layer is disposed on the oxide semiconductor channel layer. The first gate electrode is disposed on the first gate dielectric layer. The source electrode and the drain electrode are disposed at two opposite sides of the first gate electrode in a first direction respectively. The first gate electrode includes a metal material with a work function higher than 4.7 electron volts (eV). A thickness of the oxide semiconductor channel layer is smaller than one third of a length of the channel region in the first direction.

公开(公告)号：US20190081183A1

公开(公告)日：2019-03-14

申请号：US15784176

申请日：2017-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/423

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor channel layer, a second oxide semiconductor channel layer, a gate dielectric layer, and a gate electrode. The first patterned oxide semiconductor channel layer is disposed on the substrate. The second patterned oxide semiconductor channel layer is disposed on the first patterned oxide semiconductor channel layer and covers a side edge of the first patterned oxide semiconductor channel layer. The gate dielectric layer is disposed on the second patterned oxide semiconductor channel layer. A top surface of the second patterned oxide semiconductor channel layer is fully covered by the gate dielectric layer. The gate electrode is disposed on the gate dielectric layer. A projection area of the gate electrode in a thickness direction of the substrate is smaller than a projection area of the second patterned oxide semiconductor channel layer in the thickness direction.