公开(公告)号：US20230099289A1

公开(公告)日：2023-03-30

申请号：US17502015

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHEN CHEN ,  Wei Cheng ,  KOK WUN TAN ,  Shen-De Wang

IPC: H01L27/1157 ,  H01L29/06 ,  H01L27/11524

Abstract: A semiconductor memory structure includes a substrate having a device cell region and a contact forming region in proximity to the device cell region. A memory cell transistor is disposed within the device cell region. The memory cell transistor includes a gate and a charge storage structure between the gate and the substrate. The gate includes an extended portion within the contact forming region. A first spacer is disposed on a sidewall of the gate within the device cell region. A second spacer is disposed on a sidewall of the extended portion of the gate within the contact forming region. The second spacer is higher than the first spacer.

公开(公告)号：US20190131302A1

公开(公告)日：2019-05-02

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  JIANJUN YANG ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  WEICHANG LIU ,  Shen-De Wang ,  KOK WUN TAN

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L27/0924 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.