公开(公告)号：US20240321973A1

公开(公告)日：2024-09-26

申请号：US18138728

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien CHANG ,  Shen-De WANG ,  JIANJUN YANG ,  Wei Ta ,  Yuan-Hsiang Chang

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H10B41/35

CPC classification number: H01L29/404 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7816 ,  H10B41/35

Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.

公开(公告)号：US20190131302A1

公开(公告)日：2019-05-02

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  JIANJUN YANG ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  WEICHANG LIU ,  Shen-De Wang ,  KOK WUN TAN

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L27/0924 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US20170141200A1

公开(公告)日：2017-05-18

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Aaron Chen

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L27/115 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/223

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US20150270277A1

公开(公告)日：2015-09-24

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  ZHEN CHEN ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Wei Ta

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract translation: 本发明提供了一种存储单元，其包括基板，栅极介电层，图案化材料层，选择栅极和控制栅极。 栅介电层设置在基板上。 图案化材料层设置在基底上，其中图案化材料层包括垂直部分和水平部分。 选择栅极设置在栅极电介质层和图案化材料层的垂直部分的一侧。 控制栅极设置在图案化材料层的水平部分上并且在垂直部分的另一侧，其中垂直部分在选择栅极的顶部上方突出。 本发明还提供了存储单元的另一实施例及其制造方法。

公开(公告)号：US20230268437A1

公开(公告)日：2023-08-24

申请号：US17702831

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Chang ,  Shen-De Wang ,  Cheng-Hua Yang ,  LINGGANG FANG ,  JIANJUN YANG ,  Wei Ta

IPC: H01L29/78 ,  H01L29/788 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/788 ,  H01L29/42328 ,  H01L27/088 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/66689 ,  H01L29/6656

Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

公开(公告)号：US20180342394A1

公开(公告)日：2018-11-29

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  YONG BIN FAN ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.

公开(公告)号：US20160163722A1

公开(公告)日：2016-06-09

申请号：US14596227

申请日：2015-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Aaron Chen ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L27/11534 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other.

Abstract translation: 非易失性存储单元包括衬底，设置在衬底上的擦除栅极，具有顶面，分别设置在擦除栅极两侧的两个浮置栅极，分别设置在两个浮置栅极上的两个控制栅极和两个选择栅极 分别设置在两个浮动栅极的外侧，其中两个选择栅极具有彼此对称的倾斜顶部平面。