公开(公告)号：US20170141200A1

公开(公告)日：2017-05-18

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Aaron Chen

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L27/115 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/223

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US20150270277A1

公开(公告)日：2015-09-24

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  ZHEN CHEN ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Wei Ta

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract translation: 本发明提供了一种存储单元，其包括基板，栅极介电层，图案化材料层，选择栅极和控制栅极。 栅介电层设置在基板上。 图案化材料层设置在基底上，其中图案化材料层包括垂直部分和水平部分。 选择栅极设置在栅极电介质层和图案化材料层的垂直部分的一侧。 控制栅极设置在图案化材料层的水平部分上并且在垂直部分的另一侧，其中垂直部分在选择栅极的顶部上方突出。 本发明还提供了存储单元的另一实施例及其制造方法。

公开(公告)号：US20240321973A1

公开(公告)日：2024-09-26

申请号：US18138728

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien CHANG ,  Shen-De WANG ,  JIANJUN YANG ,  Wei Ta ,  Yuan-Hsiang Chang

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H10B41/35

CPC classification number: H01L29/404 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7816 ,  H10B41/35

Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.

公开(公告)号：US09583641B1

公开(公告)日：2017-02-28

申请号：US14960453

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Chih-Chien Chang ,  Jianjun Yang ,  Wen-Chuan Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7923 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66833

Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.

Abstract translation: 半导体器件的制造方法包括以下步骤。 多个选择栅极形成在半导体衬底的存储区域上。 在两个相邻的选择门之间形成两个电荷存储结构。 源区域形成在半导体衬底中，并且源区域形成在两个相邻的选择栅极之间。 在两个电荷存储结构之间形成绝缘块并形成在源极区上。 存储器栅极形成在绝缘块上，并且存储器栅极连接到两个电荷存储结构。

公开(公告)号：US08921888B2

公开(公告)日：2014-12-30

申请号：US14231659

申请日：2014-03-31

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Sung-Bin Lin

IPC: H01L29/739 ,  H01L21/266 ,  H01L29/66 ,  H01L29/73 ,  H01L29/872 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L21/266 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/66272 ,  H01L29/7304 ,  H01L29/872

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，提供半导体衬底，并且在其上限定第一区域，第二区域和第三区域。 然后，分别在第一区域和第二区域的半导体衬底中形成具有第一导电类型的第一阱。 形成与第二区域的第一阱部分重叠的半导体层。 此外，具有第二导电类型的第二阱分别形成在第三区域的半导体衬底和第二区域的第一阱中，其中第二区域的第二阱设置在半导体层下方。

公开(公告)号：US10020385B2

公开(公告)日：2018-07-10

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Zhen Chen ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

公开(公告)号：US09362125B2

公开(公告)日：2016-06-07

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

公开(公告)号：US20140206174A1

公开(公告)日：2014-07-24

申请号：US14231659

申请日：2014-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Sung-Bin Lin

IPC: H01L21/266

CPC classification number: H01L21/266 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/66272 ,  H01L29/7304 ,  H01L29/872

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，提供半导体衬底，并且在其上限定第一区域，第二区域和第三区域。 然后，分别在第一区域和第二区域的半导体衬底中形成具有第一导电类型的第一阱。 形成与第二区域的第一阱部分重叠的半导体层。 此外，具有第二导电类型的第二阱分别形成在第三区域的半导体衬底和第二区域的第一阱中，其中第二区域的第二阱设置在半导体层下方。

公开(公告)号：US10332884B2

公开(公告)日：2019-06-25

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  Jianjun Yang ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Weichang Liu ,  Shen-De Wang ,  Kok Wun Tan

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US20190131302A1

公开(公告)日：2019-05-02

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  JIANJUN YANG ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  WEICHANG LIU ,  Shen-De Wang ,  KOK WUN TAN

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L27/0924 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.