公开(公告)号：US20230268440A1

公开(公告)日：2023-08-24

申请号：US17700530

申请日：2022-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Fang-Yun Liu ,  Chien-Tung Yue ,  Kuo-Liang Yeh ,  Mu-Kai Tsai ,  Jinn-Horng Lai ,  Cheng-Hsiung Chen

IPC: H01L29/78 ,  H01L27/092 ,  H01L23/58

CPC classification number: H01L29/7845 ,  H01L27/092 ,  H01L23/585

Abstract: A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

公开(公告)号：US11488949B1

公开(公告)日：2022-11-01

申请号：US17340119

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Liang Yeh ,  Jinn-Horng Lai ,  Ching-Wen Hung ,  Chien-Tung Yue ,  Chun-Li Lin

IPC: G06F17/00 ,  H01L27/02 ,  G01R35/00

Abstract: The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.