公开(公告)号：US20250017024A1

公开(公告)日：2025-01-09

申请号：US18231448

申请日：2023-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-An HUANG ,  Shu-Hung YU ,  Chuan-Fu WANG

IPC: H10B63/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of interconnection layers disposed along a first direction, a memory element in the plurality of interconnection layers, a first conductive structure in the plurality of interconnection layers and electrically connected to the memory element, and a second conductive structure in the plurality of interconnection layers and electrically connected to the memory element. The first conductive structure includes a first conductive line and a second conductive line disposed along the first direction. The second conductive structure includes a third conductive line and a fourth conductive line disposed along the first direction. The second conductive line and the memory element are in the same interconnection layer. The third conductive line and the fourth conductive line are above the first conductive line and the second conductive line.

公开(公告)号：US20230337556A1

公开(公告)日：2023-10-19

申请号：US17747000

申请日：2022-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung YU ,  Chun-Hung CHENG ,  Chuan-Fu WANG

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L45/1633 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1253

Abstract: A resistive memory device is provided. The resistive memory device includes a first electrode, a memory structure on the first electrode, and a second electrode on the memory structure. The memory structure includes a tubular element and a pillar element. The tubular element includes oxide. The pillar element includes oxide. The pillar element is surrounded by the tubular element. The tubular element and the pillar element include different materials.

公开(公告)号：US20230057572A1

公开(公告)日：2023-02-23

申请号：US17489829

申请日：2021-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung YU ,  Chun-Hung CHENG ,  Chuan-Fu WANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.