公开(公告)号：US20240347108A1

公开(公告)日：2024-10-17

申请号：US18201213

申请日：2023-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsiu HSU ,  Yu-Huan YEH ,  Cheng-Hsiao LAI ,  Guan-Lin CHEN ,  Chuan-Fu WANG ,  Hung-Yu FAN CHIANG

IPC: G11C13/00

CPC classification number: G11C13/0064

Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.

公开(公告)号：US20210336133A1

公开(公告)日：2021-10-28

申请号：US17371376

申请日：2021-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen WANG ,  Chun-Hung CHENG ,  Chuan-Fu WANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

公开(公告)号：US20210013403A1

公开(公告)日：2021-01-14

申请号：US16504491

申请日：2019-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen WANG ,  Chun-Hung CHENG ,  Chuan-Fu WANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

公开(公告)号：US20230337556A1

公开(公告)日：2023-10-19

申请号：US17747000

申请日：2022-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung YU ,  Chun-Hung CHENG ,  Chuan-Fu WANG

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L45/1633 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1253

Abstract: A resistive memory device is provided. The resistive memory device includes a first electrode, a memory structure on the first electrode, and a second electrode on the memory structure. The memory structure includes a tubular element and a pillar element. The tubular element includes oxide. The pillar element includes oxide. The pillar element is surrounded by the tubular element. The tubular element and the pillar element include different materials.

公开(公告)号：US20230057572A1

公开(公告)日：2023-02-23

申请号：US17489829

申请日：2021-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung YU ,  Chun-Hung CHENG ,  Chuan-Fu WANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

公开(公告)号：US20250017024A1

公开(公告)日：2025-01-09

申请号：US18231448

申请日：2023-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-An HUANG ,  Shu-Hung YU ,  Chuan-Fu WANG

IPC: H10B63/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of interconnection layers disposed along a first direction, a memory element in the plurality of interconnection layers, a first conductive structure in the plurality of interconnection layers and electrically connected to the memory element, and a second conductive structure in the plurality of interconnection layers and electrically connected to the memory element. The first conductive structure includes a first conductive line and a second conductive line disposed along the first direction. The second conductive structure includes a third conductive line and a fourth conductive line disposed along the first direction. The second conductive line and the memory element are in the same interconnection layer. The third conductive line and the fourth conductive line are above the first conductive line and the second conductive line.

公开(公告)号：US20240164224A1

公开(公告)日：2024-05-16

申请号：US18082609

申请日：2022-12-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun CHANG ,  Yu-Huan YEH ,  Chuan-Fu WANG

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: A ReRAM device includes an interlayer dielectric (ILD), a lower conductive plug, a resistance-switching element (RSE) and an upper conductive plug. The ILD has an upper surface. The lower conductive plug is disposed in the ILD, and has a top surface lower than the upper surface. The RSE is disposed above the top surface and electrically contacts with the top surface. The upper conductive plug is disposed above the RSE and electrically contacts with the RSE.

公开(公告)号：US20240130254A1

公开(公告)日：2024-04-18

申请号：US18074548

申请日：2022-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Min TING ,  Chuan-Fu WANG ,  Yu-Huan YEH

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1226 ,  H01L27/2463 ,  H01L45/1253 ,  H01L45/16

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first electrode, a second electrode on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film and the second electrode are arranged along the first direction. The second semiconductor structure includes a first via and a first metal layer on the first via along a second direction and electrically connected to the first via. The first direction is perpendicular to the second direction. An upper surface of the first electrode, an upper surface of the second electrode, an upper surface of the resistive switching film and an upper surface of the first metal layer are coplanar.