公开(公告)号：US09685520B1

公开(公告)日：2017-06-20

申请号：US15355032

申请日：2016-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hsin-Ta Hsieh ,  Chun-Chia Chen ,  Chen-Chien Li ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66666

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.