公开(公告)号：US20180122705A1

公开(公告)日：2018-05-03

申请号：US15342114

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-You Chen ,  Cheng-Guo Chen ,  Kun-Yuan Wu ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo ,  Shang-Jr Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

公开(公告)号：US09634002B1

公开(公告)日：2017-04-25

申请号：US15057079

申请日：2016-02-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US09685520B1

公开(公告)日：2017-06-20

申请号：US15355032

申请日：2016-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hsin-Ta Hsieh ,  Chun-Chia Chen ,  Chen-Chien Li ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66666

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.

公开(公告)号：US09960083B1

公开(公告)日：2018-05-01

申请号：US15342114

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-You Chen ,  Cheng-Guo Chen ,  Kun-Yuan Wu ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo ,  Shang-Jr Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

公开(公告)号：US09779998B2

公开(公告)日：2017-10-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US20170221766A1

公开(公告)日：2017-08-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.