公开(公告)号：US20240413136A1

公开(公告)日：2024-12-12

申请号：US18223539

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Yi-Feng Hsu ,  Kai-Kuang Ho

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

Abstract: The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

公开(公告)号：US11495510B2

公开(公告)日：2022-11-08

申请号：US16780639

申请日：2020-02-03

Applicant: United Microelectronics Corp.

Inventor： Yu-Yuan Huang ,  Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Kai-Kuang Ho ,  Kuang-Hui Tang

IPC: H01L23/31 ,  H01L23/58 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

公开(公告)号：US20210202340A1

公开(公告)日：2021-07-01

申请号：US16780639

申请日：2020-02-03

Applicant: United Microelectronics Corp.

Inventor： YU-YUAN HUANG ,  Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Kai-Kuang Ho ,  Kuang-Hui Tang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/58

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.