SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

    公开(公告)号:US20240057486A1

    公开(公告)日:2024-02-15

    申请号:US18383473

    申请日:2023-10-24

    CPC classification number: H10N70/063 H10N70/24 H10N70/826 H10N70/841

    Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

    公开(公告)号:US20220407006A1

    公开(公告)日:2022-12-22

    申请号:US17353757

    申请日:2021-06-21

    Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

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