公开(公告)号：US20240266210A1

公开(公告)日：2024-08-08

申请号：US18116276

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chien Chung ,  Yu-Chin Huang ,  Chao-You Hung ,  Wei-Lin Liu

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer, and a metal layer is filled in the compensation groove.