公开(公告)号：US11527409B2

公开(公告)日：2022-12-13

申请号：US17016425

申请日：2020-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Liu

IPC: H01L21/033 ,  H01L21/8234

Abstract: Contact slots forming method applying photoresists include the following steps. A dielectric layer and a hard mask layer are formed on a substrate sequentially. A first patterned photoresist layer is formed over the hard mask layer, wherein the first patterned photoresist layer includes island patterns connecting to each other by connecting dummy parts. The hard mask layer is etched using the first patterned photoresist layer to form a patterned hard mask layer including island patterns connecting to each other by connecting dummy parts. A second patterned photoresist layer is formed over the patterned hard mask layer. The dielectric layer is etched using the second patterned photoresist layer and the patterned hard mask layer as a mask to form contact holes in the dielectric layer.

公开(公告)号：US20220076954A1

公开(公告)日：2022-03-10

申请号：US17016425

申请日：2020-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Liu

IPC: H01L21/033 ,  H01L21/8234

Abstract: Contact slots forming method applying photoresists include the following steps. A dielectric layer and a hard mask layer are formed on a substrate sequentially. A first patterned photoresist layer is formed over the hard mask layer, wherein the first patterned photoresist layer includes island patterns connecting to each other by connecting dummy parts. The hard mask layer is etched using the first patterned photoresist layer to form a patterned hard mask layer including island patterns connecting to each other by connecting dummy parts. A second patterned photoresist layer is formed over the patterned hard mask layer. The dielectric layer is etched using the second patterned photoresist layer and the patterned hard mask layer as a mask to form contact holes in the dielectric layer.

公开(公告)号：US20240266210A1

公开(公告)日：2024-08-08

申请号：US18116276

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chien Chung ,  Yu-Chin Huang ,  Chao-You Hung ,  Wei-Lin Liu

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer, and a metal layer is filled in the compensation groove.