公开(公告)号：US20240224529A1

公开(公告)日：2024-07-04

申请号：US18608878

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US12096635B2

公开(公告)日：2024-09-17

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US20230309309A1

公开(公告)日：2023-09-28

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H01L27/11568 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/792 ,  H01L29/40117 ,  H01L29/66833

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US20200258570A1

公开(公告)日：2020-08-13

申请号：US16290950

申请日：2019-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: G11C11/419 ,  G11C11/412

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter.

公开(公告)号：US10796752B2

公开(公告)日：2020-10-06

申请号：US16290950

申请日：2019-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter. A method of operating the static random access memory cell includes enabling the wordline transistor during a write operation, and enabling the write transistor during the write operation. The reference terminal is set to floating during the write operation.

公开(公告)号：US12225729B2

公开(公告)日：2025-02-11

申请号：US18608878

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.