公开(公告)号：US20240357817A1

公开(公告)日：2024-10-24

申请号：US18759218

申请日：2024-06-28

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC分类号： H10B43/27 ,  H01L21/28 ,  H01L21/768 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L21/76837 ,  H01L21/76843 ,  H01L29/40117 ,  H10B43/35

摘要： A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US12108602B2

公开(公告)日：2024-10-01

申请号：US18359112

申请日：2023-07-26

申请人： KIOXIA CORPORATION

发明人： Hiroki Tokuhira ,  Takahisa Kanemura ,  Shigeo Kondo ,  Michiru Hogyoku

IPC分类号： H10B43/35 ,  H01L21/28 ,  H10B43/27

CPC分类号： H10B43/35 ,  H01L29/40117 ,  H10B43/27

摘要： A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.

公开(公告)号：US12094984B2

公开(公告)日：2024-09-17

申请号：US17825359

申请日：2022-05-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Bo Shu ,  Yun-Chi Wu ,  Chung-Jen Huang

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B43/35 ,  H01L29/78

CPC分类号： H01L29/792 ,  H01L27/1237 ,  H01L29/0673 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78696 ,  H10B43/35 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

公开(公告)号：US12075623B2

公开(公告)日：2024-08-27

申请号：US18186062

申请日：2023-03-17

申请人： SK hynix Inc.

发明人： Changhan Kim ,  In Ku Kang ,  Sun Young Kim

IPC分类号： H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B43/27 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B63/845 ,  H10N70/066 ,  H10N70/231

摘要： A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

公开(公告)号：US12052870B2

公开(公告)日：2024-07-30

申请号：US17495252

申请日：2021-10-06

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Zhong Zhang ,  Wenyu Hua ,  Bo Huang ,  Zhiliang Xia

IPC分类号： H01L21/31 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L29/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L21/0337 ,  H01L21/31144 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/35

摘要： Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.

公开(公告)号：US20240234550A1

公开(公告)日：2024-07-11

申请号：US18483250

申请日：2023-10-09

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD

发明人： Sagy Charel Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam G. Geha

IPC分类号： H01L29/66 ,  B82Y10/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/7833

摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

公开(公告)号：US12029041B2

公开(公告)日：2024-07-02

申请号：US18214072

申请日：2023-06-26

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  James Pak ,  Unsoon Kim ,  Inkuk Kang ,  Sung-Taeg Kang ,  Kuo Tung Chang

IPC分类号： H10B43/40 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35

CPC分类号： H10B43/40 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35 ,  H01L29/517

摘要： A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

申请人： Kioxia Corporation

发明人： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC分类号： H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US12002523B2

公开(公告)日：2024-06-04

申请号：US17934965

申请日：2022-09-23

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari

IPC分类号： G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

CPC分类号： G11C16/3431 ,  G06F17/16 ,  G06N3/063 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/78633 ,  H01L29/7926 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

摘要： A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US20240179902A1

公开(公告)日：2024-05-30

申请号：US18082153

申请日：2022-12-15

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Lina MIAO ,  Liang XIAO ,  Yi ZHAO ,  Shu WU

IPC分类号： H10B43/20 ,  H01L21/28 ,  H01L29/792

CPC分类号： H10B43/20 ,  H01L29/40117 ,  H01L29/7926

摘要： A semiconductor device fabrication method includes providing a processing wafer. The processing wafer has core and staircase structure (SS) regions, and includes a bottom conductor layer, conductor/dielectric tier(s) over the bottom conductor layer, and a channel hole (CH) in the core region and extending approximately vertically through the conductor/dielectric tier(s). The CH includes a channel layer and a memory film surrounding the channel layer. A protrusion portion of the channel layer and a protrusion portion of the memory film extend into the bottom conductor layer. The method further includes patterning the bottom conductor layer to remove a portion of the bottom conductor layer in the core region to expose the protrusion portion of the memory film, performing etching to remove the protrusion portion of the memory film to expose the protrusion portion of the channel layer, performing impurity implantation, and performing laser activation.