公开(公告)号：US20150363534A1

公开(公告)日：2015-12-17

申请号：US14301338

申请日：2014-06-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kuo-Hsun HUANG ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G03F7/70441

Abstract: A method for post-OPC verification including of several steps is provided. First, a pre-OPC layout of an integrated circuit (IC) is received. Then, a first OPC procedure is performed to obtain a post-OPC layout of the IC. After that, a first extraction process is performed on the pre-OPC layout and a second extraction process is performed on the post-OPC layout to respectively obtain a first netlist and a second netlist by using a processor. Next, a verification process is performed by using the processor to determine whether an electrical network of the first netlist and an electrical network of the second netlist are identical. The verification process is then terminated if the electrical network of the first netlist and the electrical network of the second netlist are identical. An apparatus for post-OPC verification is also provided.

Abstract translation: 提供了一种用于后OPC验证的方法，包括几个步骤。 首先，接收到集成电路（IC）的OPC前布局。 然后，执行第一个OPC过程以获得IC的后OPC布局。 之后，对OPC前布局执行第一提取处理，并且在OPC后布局上执行第二提取处理，以通过使用处理器分别获得第一网表和第二网表。 接下来，通过使用处理器来确定第一网表的电网络和第二网表的电网是否相同来执行验证过程。 如果第一网表的电网和第二网表的电网相同，则终止验证过程。 还提供了用于后OPC验证的装置。