公开(公告)号：US09135389B2

公开(公告)日：2015-09-15

申请号：US14035952

申请日：2013-09-25

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung Chen

IPC: G06F17/50 ,  H01L25/00 ,  H01L23/522 ,  H03K19/177

CPC classification number: G06F1/10 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1774 ,  H01L2924/00

Abstract: A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided.

Abstract translation: 提供了一种适用于集成电路设计的时钟传输调整方法。 时钟传输调整方法包括以下步骤。 首先，提供包括时钟源和顺序逻辑单元的定时路径。 然后，在定时路径中插入至少一个非有效的线延迟模块以接近预定的时钟到达时间。 还提供了利用时钟传输调整方法的集成电路结构。

公开(公告)号：US09678530B2

公开(公告)日：2017-06-13

申请号：US14819444

申请日：2015-08-06

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung Chen

IPC: G06F17/50 ,  H03K19/177 ,  G06F1/10 ,  H01L23/522

CPC classification number: G06F1/10 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1774 ,  H01L2924/00

Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.

公开(公告)号：US08723249B2

公开(公告)日：2014-05-13

申请号：US13901543

申请日：2013-05-23

Applicant: United Microelectronics Corporation

Inventor： Chien-Hung Chen ,  Tzu-Ping Chen ,  Yu-Jen Chang

IPC: H01L29/82

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

Abstract: A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer, substrate and gate dielectric layer cooperatively constitute a symmetrical opening thereamong. The nitride layer has an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part is below a top surface of the gate conductive layer. The spacer is disposed on the substrate and the nitride layer. The first oxide layer is disposed among the gate conductive layer, the nitride layer and the gate dielectric layer. The second oxide layer is disposed among the gate dielectric layer, the nitride layer and the substrate.

Abstract translation: 非易失性存储器包括衬底，栅极电介质层，栅极导电层，氮化物层，间隔物，第一氧化物层和第二氧化物层。 栅极导电层，基板和栅极电介质层协同构成对称开口。 氮化物层具有L形并且形成有沿着栅极导电层的侧壁延伸的垂直部分和延伸到开口中的水平部分，其中垂直部分和水平部分形成为整体结构，并且高度 垂直部分在栅极导电层的顶表面之下。 间隔物设置在衬底和氮化物层上。 第一氧化物层设置在栅极导电层，氮化物层和栅极电介质层之间。 第二氧化物层设置在栅介质层，氮化物层和基板之间。

公开(公告)号：US20150363534A1

公开(公告)日：2015-12-17

申请号：US14301338

申请日：2014-06-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kuo-Hsun HUANG ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G03F7/70441

Abstract: A method for post-OPC verification including of several steps is provided. First, a pre-OPC layout of an integrated circuit (IC) is received. Then, a first OPC procedure is performed to obtain a post-OPC layout of the IC. After that, a first extraction process is performed on the pre-OPC layout and a second extraction process is performed on the post-OPC layout to respectively obtain a first netlist and a second netlist by using a processor. Next, a verification process is performed by using the processor to determine whether an electrical network of the first netlist and an electrical network of the second netlist are identical. The verification process is then terminated if the electrical network of the first netlist and the electrical network of the second netlist are identical. An apparatus for post-OPC verification is also provided.

Abstract translation: 提供了一种用于后OPC验证的方法，包括几个步骤。 首先，接收到集成电路（IC）的OPC前布局。 然后，执行第一个OPC过程以获得IC的后OPC布局。 之后，对OPC前布局执行第一提取处理，并且在OPC后布局上执行第二提取处理，以通过使用处理器分别获得第一网表和第二网表。 接下来，通过使用处理器来确定第一网表的电网络和第二网表的电网是否相同来执行验证过程。 如果第一网表的电网和第二网表的电网相同，则终止验证过程。 还提供了用于后OPC验证的装置。

公开(公告)号：US08956943B2

公开(公告)日：2015-02-17

申请号：US13902866

申请日：2013-05-27

Applicant: United Microelectronics Corporation

Inventor： Chien-Hung Chen ,  Tzu-Ping Chen ,  Yu-Jen Chang

IPC: H01L21/331 ,  H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.

Abstract translation: 公开了一种用于制造非易失性存储器的方法。 栅极结构形成在衬底上，并且包括栅极介电层和栅极导电层。 部分地去除栅介质层，从而在栅极导电层，基板和栅极电介质层之间形成对称的开口，并且在栅极电介质层的端侧形成空腔。 在栅极导电层的侧壁和底部上形成第一氧化物层，并且在衬底的表面上形成第二氧化物层。 形成覆盖栅极结构，第一和第二氧化物层和衬底并填充开口的氮化物材料层。 执行蚀刻处理以部分地去除氮化物材料层，从而在栅极导电层的侧壁上形成并延伸到开口中的氮化物层。