公开(公告)号：US11869854B2

公开(公告)日：2024-01-09

申请号：US17159181

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Hui-Ling Chen ,  Zhi-Rui Sheng

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01L23/5227 ,  H01L24/94 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/48139

Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

公开(公告)号：US12272662B2

公开(公告)日：2025-04-08

申请号：US17739213

申请日：2022-05-09

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Zhi-Rui Sheng ,  Hui-Ling Chen

IPC: H01L23/522 ,  H01L23/00 ,  H10D1/20 ,  H10D1/47 ,  H10D1/68

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.

公开(公告)号：US20220108946A1

公开(公告)日：2022-04-07

申请号：US17064609

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Zhi-Rui Sheng ,  Hui-Ling Chen

IPC: H01L23/522 ,  H01L49/02

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

公开(公告)号：US20220189888A1

公开(公告)日：2022-06-16

申请号：US17159181

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Hui-Ling Chen ,  Zhi-Rui Sheng

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

公开(公告)号：US11355431B2

公开(公告)日：2022-06-07

申请号：US17064609

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Zhi-Rui Sheng ,  Hui-Ling Chen

IPC: H01L23/522 ,  H01L49/02

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

公开(公告)号：US20220262752A1

公开(公告)日：2022-08-18

申请号：US17739213

申请日：2022-05-09

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Zhi-Rui Sheng ,  Hui-Ling Chen

IPC: H01L23/00 ,  H01L49/02

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.