公开(公告)号：US20130260524A1

公开(公告)日：2013-10-03

申请号：US13902866

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung CHEN ,  Tzu-Ping CHEN ,  Yu-Jen CHANG

IPC: H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.

Abstract translation: 公开了一种用于制造非易失性存储器的方法。 栅极结构形成在衬底上，并且包括栅极介电层和栅极导电层。 部分地去除栅介质层，从而在栅极导电层，基板和栅极电介质层之间形成对称的开口，并且在栅极电介质层的端侧上形成空洞。 在栅极导电层的侧壁和底部上形成第一氧化物层，并且在衬底的表面上形成第二氧化物层。 形成覆盖栅极结构，第一和第二氧化物层和衬底并填充开口的氮化物材料层。 执行蚀刻处理以部分地去除氮化物材料层，从而在栅极导电层的侧壁上形成并延伸到开口中的氮化物层。

公开(公告)号：US20140312407A1

公开(公告)日：2014-10-23

申请号：US13867125

申请日：2013-04-22

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chih-Haw LEE ,  Tzu-Ping CHEN

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

Abstract: A nonvolatile memory device comprises a substrate, a gate electrode, a single charge trapping sidewall and a source/drain region. The gate electrode is disposed on and electrically isolated from the substrate. The single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode, so as to form a non-straight angle between the substrate and the single charge trapping sidewall. The source/drain region is disposed in the substrate and adjacent to the gate electrode.

Abstract translation: 非易失性存储器件包括衬底，栅电极，单电荷俘获侧壁和源/漏区。 栅电极设置在基板上并与基板电隔离。 单电荷捕获侧壁邻近栅电极的侧壁设置并与衬底和栅电极电隔离，从而在衬底和单电荷俘获侧壁之间形成非直角。 源极/漏极区域设置在衬底中并且与栅电极相邻。

公开(公告)号：US20130248976A1

公开(公告)日：2013-09-26

申请号：US13901543

申请日：2013-05-23

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung CHEN ,  Tzu-Ping CHEN ,  Yu-Jen CHANG

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

Abstract: A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer, substrate and gate dielectric layer cooperatively constitute a symmetrical opening thereamong. The nitride layer has an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part is below a top surface of the gate conductive layer. The spacer is disposed on the substrate and the nitride layer. The first oxide layer is disposed among the gate conductive layer, the nitride layer and the gate dielectric layer. The second oxide layer is disposed among the gate dielectric layer, the nitride layer and the substrate.

Abstract translation: 非易失性存储器包括衬底，栅极电介质层，栅极导电层，氮化物层，间隔物，第一氧化物层和第二氧化物层。 栅极导电层，基板和栅极电介质层协同构成对称开口。 氮化物层具有L形并且形成有沿着栅极导电层的侧壁延伸的垂直部分和延伸到开口中的水平部分，其中垂直部分和水平部分形成为整体结构，并且高度 垂直部分在栅极导电层的顶表面之下。 间隔物设置在衬底和氮化物层上。 第一氧化物层设置在栅极导电层，氮化物层和栅极电介质层之间。 第二氧化物层设置在栅介质层，氮化物层和基板之间。