公开(公告)号：US20150340091A1

公开(公告)日：2015-11-26

申请号：US14759085

申请日：2013-12-20

Applicant: UNIVERSITY OF MAINE SYSTEM BOARD OF TRUSTEES

Inventor： Yifeng ZHU ,  Jianhui YUE

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2211/5642 ,  G11C2211/5647

Abstract: To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymmetries of writing a zero bit and a one bit. Writing a data block to PCM is divided into two separated stages, i.e., write-0 stage and write-1 stage. Without violating power constraints, during the write-0 stage, all zero bits in this data block are written to PCM at an accelerated speed; during the write-1 stage, all one bits are written to PCM, with more bits being written concurrently. In certain embodiments, the disclosed technology provides a new coding scheme to improve the speed of the write-1 stage by further increasing the number of bits that can be written to PCM in parallel.

Abstract translation: 为了提高PCM的写入性能，在某些实施例中，所公开的技术提供了一种新的写入方案，这里称为两级写入，其利用写零位和一位的速度和功率不对称性。 将数据块写入PCM被分成两个分离的阶段，即写入0阶段和写入阶段。 没有违反功率限制，在写0阶段，该数据块中的所有零位都以加速的速度写入PCM; 在写-1阶段，所有一个位都写入PCM，同时写入更多位。 在某些实施例中，所公开的技术提供了一种新的编码方案，以通过进一步增加可并行写入PCM的比特数来提高写入级的速度。