公开(公告)号：US20250126909A1

公开(公告)日：2025-04-17

申请号：US18991769

申请日：2024-12-23

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Il Kwon SHIM ,  Jeffrey PUNZALAN ,  Emmanuel ESPIRITU ,  Allan ILAGAN ,  Teddy Joaquin CARREON

IPC: H10F39/00 ,  H01L23/00

Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

公开(公告)号：US20180182801A1

公开(公告)日：2018-06-28

申请号：US15839884

申请日：2017-12-13

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Tim Thian Hwee TAN ,  Boon Pek LIEW ,  Chee Kay CHOW ,  Teddy Joaquin CARREON

IPC: H01L27/146 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.

公开(公告)号：US20210366963A1

公开(公告)日：2021-11-25

申请号：US17394365

申请日：2021-08-04

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Il Kwon SHIM ,  Jeffrey PUNZALAN ,  Emmanuel ESPIRITU ,  Allan ILAGAN ,  Teddy Joaquin CARREON

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

公开(公告)号：US20200161351A1

公开(公告)日：2020-05-21

申请号：US16687659

申请日：2019-11-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong TAN ,  Chee Kay CHOW ,  Thian Hwee TAN ,  Wedanni Linsangan MICLA ,  Enrique Jr SARILE ,  Mario Arwin FABIAN ,  Dennis TRESNADO ,  Antonino II MILANES ,  Ming Koon ANG ,  Kian Soo LIM ,  Mauro Jr. DIONISIO ,  Teddy Joaquin CARREON

IPC: H01L27/146

Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. The discontinuity enhances adhesion of the encapsulant to the protective cover.