公开(公告)号：US08436938B1

公开(公告)日：2013-05-07

申请号：US09355149

申请日：1998-05-26

申请人： Ulf Assmus ,  Michael Roth

发明人： Ulf Assmus ,  Michael Roth

IPC分类号： H04N7/00 ,  H04N11/00 ,  H04N9/475 ,  H04L25/38 ,  H04L7/00 ,  H04L12/28 ,  H04L12/56 ,  H04J3/06

CPC分类号： H04H60/04 ,  H04H60/95 ,  H04N5/073 ,  H04N21/242 ,  H04N21/4302

摘要： A device is described for receiving data transmitted using asynchronous data transmission technology, in particular audio and video data, which receives a clock signal, having a memory device (17), which stores the received data for the required period of time in order to compensate for transmission delays (Cell Delay Variation). The clock signal is sent to the memory device (17) for reading out the data. Furthermore, a method is described for receiving data signals using asynchronous data transfer technology, with the received data signals being temporarily stored and read out at the studio clock rate.

摘要翻译： 描述了一种用于接收使用异步数据传输技术（特别是音频和视频数据）发送的数据的装置，其接收时钟信号，该时钟信号具有存储装置（17），该存储装置将所接收的数据存储在所需时间段内以便补偿 用于传输延迟（单元延迟变化）。 时钟信号被发送到用于读出数据的存储器件（17）。 此外，描述了一种使用异步数据传输技术接收数据信号的方法，其中所接收的数据信号被暂时存储并以录音室时钟速率读出。

公开(公告)号：US5708686A

公开(公告)日：1998-01-13

申请号：US618437

申请日：1996-03-15

申请人： Ulf Assmus ,  Willy Heckwolf ,  Detlef Martin ,  Dieter Becker

发明人： Ulf Assmus ,  Willy Heckwolf ,  Detlef Martin ,  Dieter Becker

IPC分类号： H04J3/06 ,  H04L12/70 ,  H04L7/00

CPC分类号： H04J3/0632 ,  H04L2012/5616 ,  H04L2012/5674

摘要： In a method for receiver-side clock recovery for digital signals having a constant bit rate following cell-structured, asynchronous transmission with pauses of different length between individual cells using the loading state of an FIFO memory into which the received digital signals are written, at the start of a transmission the digital signals are initially read with a received clock into the FIFO memory holding multiple cells of the received signals until the FIFO memory is half filled. The digital signals written into the FIFO memory are read out with a readout clock whose frequency is smaller than the frequency of the received clock. During the readout a signal for controlling the frequency of the readout clock is derived from the respective loading state of the FIFO memory.

摘要翻译： 在用于数字信号的接收机侧时钟恢复的方法中，在使用所接收的数字信号写入到其中的FIFO存储器的加载状态之后，在具有小区结构的异步传输之后，具有恒定位速率的数字信号，其中各个单元之间具有不同长度的暂停， 开始传输数字信号最初以接收的时钟读取到保存接收信号的多个单元的FIFO存储器中，直到FIFO存储器被半充满。 写入FIFO存储器的数字信号用频率小于接收时钟的频率的读出时钟读出。 在读出期间，从FIFO存储器的各自的加载状态导出用于控制读出时钟的频率的信号。