公开(公告)号：US20060119624A1

公开(公告)日：2006-06-08

申请号：US11297123

申请日：2005-12-07

申请人： Dirk Wendel ,  Ulrich Langenkamp ,  Marko Hahn

发明人： Dirk Wendel ,  Ulrich Langenkamp ,  Marko Hahn

IPC分类号： G09G5/00

CPC分类号： G06T3/40

摘要： A graphic character that has a character matrix with a number of character units that are indivisible at least in either a horizontal direction or a vertical direction is scaled by dividing the character matrix into one first and at least one second character segment, each comprising at least one of the character units. The first character segment is symmetrically scaled using a first scaling factor and the second character segment is scaled using a second scaling factor different from the first scaling factor.

公开(公告)号：US5038118A

公开(公告)日：1991-08-06

申请号：US578029

申请日：1990-09-05

申请人： Ulrich Langenkamp

发明人： Ulrich Langenkamp

IPC分类号： H03K3/03 ,  H03K3/354

CPC分类号： H03K3/354 ,  H03K3/0315

摘要： A circuit configuration of an integratable and controllable ring oscillator for generating a clock signal includes first and second stages being connected between supply terminals and having input and output terminals. The output terminal of the first stage is connected to the input terminal of the second stage. An inverter is connected between the output terminal of the second stage and the input terminal of the first stage. The input terminal of the second stage supplies a clock signal. Each of the stages includes first and second transistors having load paths connected between the supply terminals in a series circuit with a connecting point between the transistors. The second transistor has a gate terminal connected to the input terminal. The first transistor determines the frequency of the clock signal, is controllable in accordance with a control variable and acts as a current source. A capacitor has one terminal connected to the connecting point and another terminal connected to a fixed potential. A decoupling stage is connected between the output terminal and the connecting point.

摘要翻译： 用于产生时钟信号的可积分和可控环形振荡器的电路配置包括连接在电源端子之间并具有输入和输出端子的第一和第二级。 第一级的输出端连接到第二级的输入端。 逆变器连接在第二级的输出端和第一级的输入端之间。 第二级的输入端提供时钟信号。 每个级包括第一和第二晶体管，其具有连接在具有晶体管之间的连接点的串联电路中的电源端子之间的负载路径。 第二晶体管具有连接到输入端的栅极端子。 第一晶体管确定时钟信号的频率，可根据控制变量进行控制，并作为电流源。 电容器有一个端子连接到连接点，另一个端子连接到固定电位。 在输出端子和连接点之间连接一个去耦阶段。

公开(公告)号：US4656513A

公开(公告)日：1987-04-07

申请号：US676556

申请日：1984-11-30

申请人： Ulrich Langenkamp

发明人： Ulrich Langenkamp

IPC分类号： H04N7/08 ,  H04N7/035 ,  H04N7/081 ,  H04N7/088 ,  H04N7/087

CPC分类号： H04N7/0355 ,  H04N7/088 ,  H04N7/0882

摘要： A data slicer circuit for separating and recovering digital teletext signals from a demodulated composite color signal derives the slicing level by using a framing code detector and a gating pulse having an active phase during horizontal and color sync pulses. By an adder or a multiplier, a start value is formed at the beginning of each picture line. A square wave reference signal is formed which is subtracted from the start value containing composite color signal. From the difference signal, a digital automatic control system forms the slicing level.

摘要翻译： 用于从解调的复合彩色信号中分离和恢复数字图文信号的数据限幅器电路通过在水平和彩色同步脉冲期间使用成帧码检测器和具有有效相位的选通脉冲来导出限幅电平。 通过加法器或乘法器，在每个图像行的开始处形成起始值。 形成从包含复合颜色信号的起始值减去的方波参考信号。 从差分信号，数字自动控制系统形成切片级。

公开(公告)号：US07532216B2

公开(公告)日：2009-05-12

申请号：US11297123

申请日：2005-12-07

申请人： Dirk Wendel ,  Ulrich Langenkamp ,  Marko Hahn

发明人： Dirk Wendel ,  Ulrich Langenkamp ,  Marko Hahn

IPC分类号： G06T11/00 ,  G09G5/26 ,  G09G5/00

CPC分类号： G06T3/40

摘要： A graphic character that has a character matrix with a number of character units that are indivisible at least in either a horizontal direction or a vertical direction is scaled by dividing the character matrix into one first and at least one second character segment, each comprising at least one of the character units. The first character segment is symmetrically scaled using a first scaling factor and the second character segment is scaled using a second scaling factor different from the first scaling factor.

摘要翻译： 具有至少在水平方向或垂直方向上不可分割的具有多个字符单元的字符矩阵的图形字符通过将字符矩阵划分成一个第一和至少一个第二字符段来缩放，每个字符段至少包括 其中一个角色单位。 使用第一缩放因子对第一字符段进行对称缩放，并且使用不同于第一缩放因子的第二缩放因子来缩放第二字符段。

公开(公告)号：US4653055A

公开(公告)日：1987-03-24

申请号：US682510

申请日：1984-12-17

申请人： Liubomir Micic ,  Thomas Fischer ,  Ulrich Langenkamp

发明人： Liubomir Micic ,  Thomas Fischer ,  Ulrich Langenkamp

IPC分类号： G06F11/10 ,  H03M13/00 ,  H04N7/035 ,  G06F11/08

CPC分类号： H04N7/0357

摘要： With this correcting method, errors in bytes are corrected successively. To this end, the signal resulting from the parity check is stored into a page memory, along with the character bits of each byte. The parity check signal replaces the parity bit of each byte. Two successively received identical pages are stored together with their parity check bits into first and second segments of the page memory. The two pages are compared for equality of the character bits and parity check bits. The result of the comparison is evaluated as follows. In case of equality and correct parity, the byte stored in the first segment will remain unchanged; in case of inequality of the two bytes and correct parity of one of the two bytes, the byte having correct parity will be stored into or remain stored in the first segment; in case of inequality and incorrect parity of the two bytes, no change will be made in the first segment; in case inequality and correct parity of the two bytes, the byte in the first segment will be replaced by a blank byte. The next received identical page but one is stored into the second segment by overwriting, and the correction is repeated with this byte. By this method, single errors are detected and corrected and double errors are detected and replaced by a blank character. In a preferred embodiment with a third segment of the page memory, storage of the third received identical page, and corresponding comparisons of the bytes in the three segments, the method is extended so that double errors are corrected as well.

摘要翻译： 利用这种校正方法，连续校正字节错误。 为此，将奇偶校验产生的信号与每个字节的字符位一起存储到页存储器中。 奇偶校验信号代替每个字节的奇偶校验位。 两个连续接收的相同的页面与它们的奇偶校验位一起存储在页面存储器的第一和第二段中。 比较两个页面的字符位和奇偶校验位的相等性。 比较结果如下评估。 在相等和正确的奇偶校验的情况下，存储在第一段中的字节将保持不变; 在两个字节的不等式和两个字节之一的正确奇偶校验的情况下，具有正确奇偶校验的字节将被存储到或保持在第一段中; 在两个字节的不平等和不正确的奇偶校验的情况下，在第一段中不会改变; 在两个字节的不等式和正确奇偶校验的情况下，第一段中的字节将被一个空白字节替换。 下一个接收到的相同页面，但是通过重写将其存储到第二段中，并且用该字节重复校正。 通过这种方法，检测和纠正单个错误，并检测双重错误并用空白字符替换。 在具有页存储器的第三段，第三接收的相同页的存储以及三段中的字节的对应比较的优选实施例中，该方法被扩展，从而也纠正了双重错误。

公开(公告)号：US4618788A

公开(公告)日：1986-10-21

申请号：US580512

申请日：1984-02-15

申请人： Reiner Backes ,  Ulrich Langenkamp

发明人： Reiner Backes ,  Ulrich Langenkamp

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03L7/00

CPC分类号： H03K5/131 ,  H03K2005/00045 ,  H03K2005/00097

摘要： A delay circuit provides adjustable delay in constant increments. In order to achieve adjustable but constant delay times of a chain of inverter pairs, each pair is completed by a capacitor, a third inverter, and a transfer transistor the gate of which is fed by a voltage controlling the pair delay time. This voltage is generated by a control circuit measuring the actual delay time of the chain with respect to the period of a constant clock signal.

摘要翻译： 延迟电路以恒定的增量提供可调延迟。 为了实现一对逆变器对的可调但恒定的延迟时间，每一对由电容器，第三反相器和转移晶体管完成，其栅极通过控制对延迟时间的电压馈送。 该电压由控制电路产生，该控制电路相对于恒定时钟信号的周期测量链的实际延迟时间。