公开(公告)号：US06472696B1

公开(公告)日：2002-10-29

申请号：US09645763

申请日：2000-08-25

申请人： Ulrich Zimmermann ,  Thomas Böhm ,  Manfred Hain ,  Armin Kohlhase ,  Yoichi Otani ,  Andreas Rusch ,  Alexander Trüby

发明人： Ulrich Zimmermann ,  Thomas Böhm ,  Manfred Hain ,  Armin Kohlhase ,  Yoichi Otani ,  Andreas Rusch ,  Alexander Trüby

IPC分类号： H01L2710

CPC分类号： H01L27/11273 ,  H01L27/112

摘要： The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

摘要翻译： 存储单元配置具有设置在半导体衬底中的大量存储单元，并且具有在半导体衬底的主面中在纵向方向上平行延伸的位线沟槽，其底部在每种情况下都具有第一导电 区域被提供，其峰值在每种情况下具有与第一导电区域相同的导电类型的第二导电区域，并且在其每一种情况下壁的中间位置的沟道区域为0; 并且具有通过特定位线沟槽沿着半导体衬底的主面在横向上延伸的字线，以激活在其中设置的晶体管。 另外的掺杂剂被引入位于字线之间的位线沟槽的沟槽壁中，以便在其上增加对应的晶体管导通电压以抑制漏电流。

公开(公告)号：US07030017B2

公开(公告)日：2006-04-18

申请号：US10692234

申请日：2003-10-23

申请人： Mark Hollatz ,  Klaus-Dieter Morhard ,  Alexander Trüby ,  Dirk Többen

发明人： Mark Hollatz ,  Klaus-Dieter Morhard ,  Alexander Trüby ,  Dirk Többen

IPC分类号： H01L21/302

CPC分类号： H01L21/31055 ,  H01L21/31053 ,  H01L21/76229

摘要： The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B1) is formed on the layer to be planarized above the first sub-structure (AA′) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M1; O1) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M1) of the grid, is created by the etching step, using the pre-planarization mask.

摘要翻译： 本发明涉及一种用于平面化半导体结构的方法，该半导体结构包括其中提供几个子结构（STI; AA; AA'; AA“）的衬底。 具有具有平面区域（PS）和第一沟槽区域（DT）的第一子结构（AA'）的所述子结构（STI; AA; AA'; AA“））。 在半导体结构上施加待平坦化的层，所述层在第一子结构（AA'）的第一沟槽区（DT）上方具有合适的凹槽。 该方法包括以下步骤：通过蚀刻步骤对待平坦化的层进行预平面化，使用预平面化掩模，然后通过化学机械抛光步骤平面化待平坦化的层。 根据本发明，通过预平面化掩模在第一子结构（AA'）上方的平坦化层上形成第一区域（B 1），所述区域具有预定的屏蔽和未屏蔽部分的网格 （M 1; O 1）以分别覆盖第一沟槽区域（DT）和平面区域（PS）的方式布置，以及用于化学机械抛光步骤的支撑结构，其对应于掩模部分 M 1）通过使用预平面化掩模的蚀刻步骤产生。