公开(公告)号：US20150236150A1

公开(公告)日：2015-08-20

申请号：US14183541

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Shing Chen ,  Ming-Hui Chang ,  Wei-Ting Wu ,  Ying-Chou Lai ,  Horng-Nan Chern ,  Chorng-Lih Young ,  Chin-Sheng Yang

IPC: H01L29/78 ,  H01L29/45 ,  H03K3/012 ,  H01L29/10 ,  H01L29/49 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7835

Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Abstract translation: 提供一种半导体器件，包括P型衬底，P型第一阱区，N型第二阱区，栅极，N型源极和漏极区，虚拟栅极和N型阱阱区域 。 第一阱区位于衬底中。 第二阱区位于靠近第一阱区的衬底中。 栅极位于基板上并且覆盖第一阱区域的一部分和第二阱区域的一部分。 源极区位于栅极一侧的第一阱区中。 漏极区域位于栅极另一侧的第二阱区域中。 虚拟栅极位于栅极和漏极区域之间的衬底上。 深井区域位于基板中并围绕第一和第二井区域。 还提供了一种半导体器件的操作方法。

公开(公告)号：US09490360B2

公开(公告)日：2016-11-08

申请号：US14183541

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Shing Chen ,  Ming-Hui Chang ,  Wei-Ting Wu ,  Ying-Chou Lai ,  Horng-Nan Chern ,  Chorng-Lih Young ,  Chin-Sheng Yang

IPC: H01L21/761 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7835

Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Abstract translation: 提供一种半导体器件，包括P型衬底，P型第一阱区，N型第二阱区，栅极，N型源极和漏极区，虚拟栅极和N型阱阱区域 。 第一阱区位于衬底中。 第二阱区位于靠近第一阱区的衬底中。 栅极位于基板上并且覆盖第一阱区域的一部分和第二阱区域的一部分。 源极区位于栅极一侧的第一阱区中。 漏极区域位于栅极另一侧的第二阱区域中。 虚拟栅极位于栅极和漏极区域之间的衬底上。 深井区域位于基板中并围绕第一和第二井区域。 还提供了一种半导体器件的操作方法。