公开(公告)号：US20230025163A1

公开(公告)日：2023-01-26

申请号：US17404939

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen Wen Gong ,  Xiaofei Han ,  Chow Yee Lim ,  Hong Liao ,  Jun Qian

IPC: H01L21/308 ,  H01L27/11556

Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.

公开(公告)号：US20160225696A1

公开(公告)日：2016-08-04

申请号：US14667108

申请日：2015-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiao-Fei Han ,  Jun Qian ,  Ju-Bao Zhang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/53295 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a through silicon via hole, an interlayer dielectric, a liner layer and a conductor. The through silicon via hole is formed in the substrate. The interlayer dielectric is formed on the substrate. The interlayer dielectric defines an opening corresponding to the through silicon via hole. The interlayer dielectric comprises a bird beak portion near the through silicon via hole. The liner layer is formed on a bottom and a sidewall of the through silicon via hole. The conductor is filled in the through silicon via hole and the opening.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，穿硅通孔，层间电介质，衬垫层和导体。 贯穿硅通孔形成在基板中。 在基板上形成层间电介质。 层间电介质限定对应于贯穿硅通孔的开口。 层间电介质包括靠近硅通孔的鸟嘴部分。 衬垫层形成在贯通硅通孔的底部和侧壁上。 导体填充在硅通孔和开口中。

公开(公告)号：US09524923B2

公开(公告)日：2016-12-20

申请号：US14667108

申请日：2015-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiao-Fei Han ,  Jun Qian ,  Ju-Bao Zhang

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/53295 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a through silicon via hole, an interlayer dielectric, a liner layer and a conductor. The through silicon via hole is formed in the substrate. The interlayer dielectric is formed on the substrate. The interlayer dielectric defines an opening corresponding to the through silicon via hole. The interlayer dielectric comprises a bird beak portion near the through silicon via hole. The liner layer is formed on a bottom and a sidewall of the through silicon via hole. The conductor is filled in the through silicon via hole and the opening.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，穿硅通孔，层间电介质，衬垫层和导体。 贯穿硅通孔形成在基板中。 在基板上形成层间电介质。 层间电介质限定对应于贯穿硅通孔的开口。 层间电介质包括靠近硅通孔的鸟嘴部分。 衬垫层形成在贯通硅通孔的底部和侧壁上。 导体填充在硅通孔和开口中。