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公开(公告)号：US20180292848A1
公开(公告)日：2018-10-11
申请号：US15607266
申请日：2017-05-26
Applicant: United Microelectronics Corp.
Inventor： Chai-Wei Fu , Cheng-Hsiao Lai , Ying-Ting Lin , Yuan-Hui Chen , Ya-Nan Mou , Yung-Hsiang Lin , Hsueh-Chen Cheng
Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.
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公开(公告)号：US10095251B1
公开(公告)日：2018-10-09
申请号：US15607266
申请日：2017-05-26
Applicant: United Microelectronics Corp.
Inventor： Chai-Wei Fu , Cheng-Hsiao Lai , Ying-Ting Lin , Yuan-Hui Chen , Ya-Nan Mou , Yung-Hsiang Lin , Hsueh-Chen Cheng
Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.
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