公开(公告)号：US20140091282A1

公开(公告)日：2014-04-03

申请号：US13788321

申请日：2013-03-07

申请人： Universal Display Corporation (027166)

发明人： Peter Levermore ,  Huiqing Pang ,  Emory Krall ,  Rajan Kamala ,  Ruiqing Ma ,  Paul E. Burrows

IPC分类号： H01L51/56 ,  H01L51/52

CPC分类号： H01L51/5203 ,  C23C14/042 ,  C23C14/24 ,  H01L27/3202 ,  H01L27/3204 ,  H01L27/3279 ,  H01L27/329 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/50 ,  H01L51/5016 ,  H01L51/5212 ,  H01L51/5228 ,  H01L51/56 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01L2251/5392 ,  H05B33/10

摘要： Systems and methods for the design and fabrication of OLEDs, including high-performance large-area OLEDs, are provided. Variously described fabrication processes may be used to deposit and pattern bus lines with a smooth profile and a gradual sidewall transition. Such smooth profiles may, for example, reduce the probability of electrical shorting at the bus lines. Accordingly, in certain circumstances, an insulating layer may no longer be considered essential, and may be optionally avoided altogether. In cases where an insulating layer is not used, further enhancements in the emissive area and shelf life of the device may be achieved as well. According to aspects of the invention, bus lines such as those described herein may be deposited, and patterned, using vapor deposition such as vacuum thermal evaporation (VTE) through a shadow mask, and may avoid multiple photolithography steps. Other vapor deposition systems and methods may include, among others, sputter deposition, e-beam evaporation and chemical vapor deposition (CVD). A final profile of the bus line may substantially correspond to the profile as deposited.

摘要翻译： 提供了用于设计和制造OLED的系统和方法，包括高性能大面积OLED。 可以使用各种描述的制造工艺来沉积和模拟具有平滑轮廓和逐渐侧壁转变的总线。 这样的平滑轮廓可以例如降低在总线线路处短路的可能性。 因此，在某些情况下，绝缘层可能不再被认为是必要的，并且可以完全可选地避免。 在不使用绝缘层的情况下，也可以实现装置的发射面积和保存期限的进一步增强。 根据本发明的方面，可以使用诸如真空热蒸发（VTE）之类的气相沉积通过荫罩来沉积和图案化这样描述的总线，并且可以避免多个光刻步骤。 其他气相沉积系统和方法可以包括溅射沉积，电子束蒸发和化学气相沉积（CVD）。 总线的最终配置文件可以基本上对应于保存的配置文件。