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    Method and system for oscilloscope triggering
    1.
    发明授权
    Method and system for oscilloscope triggering 有权

    公开(公告)号：US10775418B2

    公开(公告)日：2020-09-15

    申请号：US15859987

    申请日：2018-01-02

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

    Inventor： Jun Jiang ,  Lianping Guo ,  Xiaoman Jiao ,  Wuhuang Huang ,  Hao Zeng ,  Feng Tan

    IPC: G01R13/02

    Abstract: The present invention provides a method and system for oscilloscope triggering. The power spectrum entropy threshold Gp and the singular spectrum entropy threshold Gs are obtained by calculating the averages of the power spectrum entropy Hi and the singular spectrum entropy Ei of the first a waveform data frames respectively. Then, for the waveform data frame xa+1(τ) and thereafter, If the power spectrum entropy Hi is greater than power spectrum entropy threshold Gp and the singular spectrum entropy Ei is greater than the singular spectrum entropy threshold Gs, the waveform data frame xi(τ) is an abnormal signal, the second trigger occurs, storing and displaying the waveform data frame. Thus the storage and display of abnormal signal is realized.

    Method for equivalent high sampling rate FIR filtering based on FPGA
    2.
    发明授权
    Method for equivalent high sampling rate FIR filtering based on FPGA 有权

    公开(公告)号：US10998885B2

    公开(公告)日：2021-05-04

    申请号：US16163596

    申请日：2018-10-18

    Applicant: University of Electronic Science and Technology of China

    Inventor： Lianping Guo ,  Hao Zeng ,  Feng Tan ,  Duyu Qiu ,  Xianggong Guo ,  Yu Li

    IPC: H03H17/06 ,  H03H17/02 ,  H03H17/00

    Abstract: The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock cycle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L′ periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.

    Method for oscilloscope 3D mapping in scan mode
    3.
    发明授权
    Method for oscilloscope 3D mapping in scan mode 有权

    公开(公告)号：US10677817B2

    公开(公告)日：2020-06-09

    申请号：US15879146

    申请日：2018-01-24

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

    Inventor： Kuojun Yang ,  Wuhuang Huang ,  Peng Ye ,  Qinchuan Zhang ,  Hao Zeng ,  Duyu Qiu ,  Jun Jiang ,  Huiqing Pan ,  Lianping Guo ,  Feng Tan

    IPC: G01R13/02

    Abstract: A method for oscilloscope 3D mapping in scan mode. The input signal is acquired using a real-time sampling rate which is Dr times higher, thus more sampling points, i.e. Dr acquired data can be obtained during the time interval between two consecutive horizontal pixels. The Dr acquired data are mapped into a same column of the screen to implement fluorescent waveform display. In addition, to realize the scanning display, a flag X is introduced into the three-dimensional database, when the screen refresh signal arrives, the first Ds acquired data are read out from the unread acquired data in FIFO memory. The three-dimensional database is updated from the flag X, which make the leftmost waveform always be the oldest waveform, the rightmost waveform always be the newest waveform. Thus the 3D mapping is realized in scan mode, letting the DSO have a fluorescent waveform display at slow time-base.

    Method and apparatus for automatically adjusting the hold-off time of a DSO
    4.
    发明授权
    Method and apparatus for automatically adjusting the hold-off time of a DSO 有权

    公开(公告)号：US10823762B2

    公开(公告)日：2020-11-03

    申请号：US16005763

    申请日：2018-06-12

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

    Inventor： Qinchuan Zhang ,  Feng Tan ,  Huiqing Pan ,  Hao Zeng ,  Luonan Zheng

    IPC: G01R13/02

    Abstract: The present invention provides a method and apparatus for automatically adjusting the hold-off time of a DSO based on real-time cycle measurements of the system trigger signal: obtaining a cycle sequence by measuring the system trigger signal, the maximum cycle and minimum cycle, then judging the difference of the maximum cycle and minimum cycle: if the difference is greater than a threshold set by user, setting the hold-off time to the maximum cycle, the minimum cycle or the median cycle, then returning; otherwise terminating the adjustment of the hold-off time. At this point, the hold-off time is correctly set. Therefore, the present invention reduces the complexity and time consumption of the hold-off adjustment, and allows the test signal to be quickly and stably displayed on screen of DSO, meanwhile, which makes the trigger adjustment of DSO more convenient.

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