公开(公告)号：US10998885B2

公开(公告)日：2021-05-04

申请号：US16163596

申请日：2018-10-18

Applicant: University of Electronic Science and Technology of China

Inventor： Lianping Guo ,  Hao Zeng ,  Feng Tan ,  Duyu Qiu ,  Xianggong Guo ,  Yu Li

IPC: H03H17/06 ,  H03H17/02 ,  H03H17/00

Abstract: The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock cycle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L′ periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.