公开(公告)号：US20220367712A1

公开(公告)日：2022-11-17

申请号：US17367442

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Liu YUAN ,  Zhao WANG ,  Wenliang LIU ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.