公开(公告)号：US20240112914A1

公开(公告)日：2024-04-04

申请号：US18121609

申请日：2023-03-15

Applicant: University of Electronic Science and Technology of China

Inventor： Bo ZHANG ,  Teng LIU ,  Wentong ZHANG ,  Nailong HE ,  Sen ZHANG ,  Ming QIAO ,  Zhaoji LI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/32139

Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

公开(公告)号：US20210074699A1

公开(公告)日：2021-03-11

申请号：US16839089

申请日：2020-04-03

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Linrong HE ,  Yi LI ,  Chunlan LAI ,  Bo Zhang

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739

Abstract: An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

公开(公告)号：US20250081553A1

公开(公告)日：2025-03-06

申请号：US18388870

申请日：2023-11-13

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Jue LI ,  Zesheng SHI ,  Daoming SHEN ,  Bo ZHANG

IPC: H01L29/06

Abstract: A power semiconductor device, including a cell region, a transition region, and a terminal region. The transition region is located between the cell region and the terminal region of the device. A first conduction type substrate, a first conduction type epitaxial layer located above the first conduction type substrate, and a first conduction type buffer layer located in the first conduction type epitaxial layer are jointly arranged at the bottoms of the cell region, the transition region, and the terminal region of the device. In a high-current application, since the cell region occupies the largest area of a chip, in a case that breakdown can occur in the cell region and the current can be discharged through the cell region. On the basis of ensuring the BV of the terminal region, a silicon layer step is formed by elevating the position of a top structure of the terminal region.

公开(公告)号：US20240395930A1

公开(公告)日：2024-11-28

申请号：US18382561

申请日：2023-10-23

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Yue GAO ,  Jiawei WANG ,  Dingxiang MA ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

公开(公告)号：US20210305051A1

公开(公告)日：2021-09-30

申请号：US17004031

申请日：2020-08-27

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Shida DONG ,  Zhengkang WANG ,  Dong FANG ,  Zhuo WANG ,  Bo ZHANG

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/765 ,  H01L29/66

Abstract: A metal wiring method for reducing gate resistance of a narrow control gate structure, wherein the gate structure is etched with first gate electrodes and second gate electrodes at regular intervals and kept with complete gate electrodes at regular intervals, thereby constituting a structure in which the first and second gate electrodes and the complete gate electrodes are spaced apart. A first contact hole is etched on the complete gate electrode to draw out metal as a first metal layer. A second contact hole is etched on a source region and a split gate to draw out metal as a second metal layer. These two metal layers are separated by a dielectric layer. A multi-point contact of the first layer of metal with the gate electrode in a Y direction reduces the gate resistance caused by an excessively long path in the Y direction of a control gate electrode.

公开(公告)号：US20250107137A1

公开(公告)日：2025-03-27

申请号：US18398222

申请日：2023-12-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Jiawei WANG ,  Dingxiang MA ,  Yue GAO ,  Gen LIU ,  Shengduo WANG ,  Yuanqing YE ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A lateral power semiconductor device layout and a device structure belong to the technical field of power semiconductor devices. A method for designing a lateral power semiconductor device layout with high integrity and high cell density has the following advantages of reducing a specific on-resistance of the device, increasing a width of a channel per unit area, improving the current capability of the device, optimizing the static characteristic of the device, reducing the area of a drain region and the parasitic capacitance of the device, reducing the delay time of a cell switch caused by an excessively long gate electrode of a traditional finger cell, optimizing the dynamic characteristic of the device, optimizing the cell edge of the device and the curvature effect of a terminal, and reducing the pre-breakdown risk of the device.

公开(公告)号：US20190304966A1

公开(公告)日：2019-10-03

申请号：US16017978

申请日：2018-06-25

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Zhao QI ,  Jiamu XIAO ,  Longfei LIANG ,  Danye LIANG ,  Bo ZHANG

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

公开(公告)号：US20220367712A1

公开(公告)日：2022-11-17

申请号：US17367442

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Liu YUAN ,  Zhao WANG ,  Wenliang LIU ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

公开(公告)号：US20220352304A1

公开(公告)日：2022-11-03

申请号：US17351267

申请日：2021-06-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Shuhao ZHANG ,  Zhangyi'an YUAN ,  Dican HOU ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.

公开(公告)号：US20210336052A1

公开(公告)日：2021-10-28

申请号：US17005354

申请日：2020-08-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Zhengkang WANG ,  Shida DONG ,  Bo ZHANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.