公开(公告)号：US20030147359A1

公开(公告)日：2003-08-07

申请号：US10338733

申请日：2003-01-09

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Murphy Chen

IPC: H04B003/36

CPC classification number: H04B3/36

Abstract: This invention discloses a long-distance network transmission structure and associated device thereof. The invention utilizes the CAT-5 transmission line network to achieve a high-speed long-distance network tranceiving. A DSP PHY (Digital Signal Processing Physical) is employed in the long-distance network transmission structure to receive a data signal from the transmission line. The signal is then driven to clients with a common PHY without DSP capability or a DSP PHY. Through such a DSP PHY, the signal can be transmitted over 3000 ft and the transmission rate can reach duplex 100 Mbps. Two pairs of cords inside the CAT-5 network transmission line are used to provide the full duplex data tranceiving and the other two spare cords provide electrical power for a repeater. Therefore, the long-distance transmission structure and associated device thereof can effectively reduce the cost for both network service providers and clients and facilitate the installation.

Abstract translation: 本发明公开了一种长距离网络传输结构及其相关装置。 本发明利用CAT-5传输线网络实现高速长途网络的恍惚。 在长距离网络传输结构中采用DSP PHY（数字信号处理物理）来从传输线接收数据信号。 然后，该信号被驱动到具有不具有DSP能力的公共PHY的客户端或DSP PHY。 通过这样的DSP PHY，信号可以在3000英尺以上传输，传输速率可以达到双工100 Mbps。 CAT-5网络传输线内的两条电线用于提供全双工数据保护，另外两条备用电缆为中继器提供电源。 因此，长距离传输结构及其相关设备可以有效降低网络服务提供商和客户端的成本，便于安装。

公开(公告)号：US20030191895A1

公开(公告)日：2003-10-09

申请号：US10400523

申请日：2003-03-28

Applicant: VIA TECHNOLOGIES, INC

Inventor： Murphy Chen ,  Perlman Hu

IPC: G06F012/00

CPC classification number: G06F5/10 ,  G06F12/023 ,  G06F2205/106

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

公开(公告)号：US20030172327A1

公开(公告)日：2003-09-11

申请号：US10352439

申请日：2003-01-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Murphy Chen ,  Perlman Hu

IPC: G11B005/00 ,  G06K005/04 ,  G11B020/20 ,  G01R031/28

CPC classification number: H03L7/06 ,  G01R31/2882 ,  G01R31/31727 ,  G11B20/1403

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract translation: 公开了一种用于测试嵌入式锁相环（PLL）电路的方法和装置。 将第一频率的第一时钟信号提供给嵌入式锁相环（PLL）电路以供测试者测试，以便响应于第一时钟信号的第一时钟信号，由嵌入式PLL电路产生PLL时钟信号 第一频率 PLL时钟信号与第二频率的第二时钟信号一起被输入到测试电路。 然后，利用第二频率的第二时钟信号对PLL时钟信号进行采样，以产生第一采样信号。 第二频率与第一频率具有第一相关性。 根据第一采样信号确定嵌入式PLL电路是否处于正常工作状态。