公开(公告)号：US20150341658A1

公开(公告)日：2015-11-26

申请号：US14818886

申请日：2015-08-05

申请人： VIA Telecom Co., Ltd.

发明人： Yinglai XI ,  Qiang LI ,  Jumei LI ,  Jianbin HE ,  Jinfeng ZHOU ,  Zhichong CHEN ,  Liu YANG ,  Dong LI

IPC分类号： H04N19/547 ,  H04N19/122 ,  H04N19/82 ,  H04N19/117

CPC分类号： H04N19/547 ,  H04N19/117 ,  H04N19/122 ,  H04N19/433 ,  H04N19/50 ,  H04N19/523 ,  H04N19/533 ,  H04N19/56 ,  H04N19/82

摘要： An in-loop filtering acceleration circuit applied in a video codec system supporting the H.264 standard and the VC-1 standard is provided. The circuit includes multiple one-dimensional (1D) filters configured to perform a filtering process; and a filter selection unit configured to select one of the 1D filters according to the value of the boundary strength to perform the filtering processing to the reconstructed macroblock. The in-loop filtering acceleration circuit further divides the reconstructed macroblock into multiple 8×8 blocks and multiple 4×4 blocks, performs the filtering process to horizontal edges of the 8×8 blocks the reconstructed macroblock row by row from bottom to top, and performs the filtering process to horizontal edges of the 4×4 blocks row by row from top to bottom.

摘要翻译： 提供了一种应用于支持H.264标准和VC-1标准的视频编解码器系统中的环路滤波加速电路。 该电路包括被配置为执行滤波处理的多个一维（1D）滤波器; 以及滤波器选择单元，被配置为根据边界强度的值来选择一个1D滤波器，以对重建的宏块执行滤波处理。 环路滤波加速电路进一步将重建的宏块划分为多个8×8块和多个4×4块，对重建的宏块逐个从底部到顶部的8×8块的水平边缘进行滤波处理， 从上到下逐行执行4×4块的水平边缘的过滤处理。