公开(公告)号：US20150195522A1

公开(公告)日：2015-07-09

申请号：US14458524

申请日：2014-08-13

Applicant: VIA Telecom Co., Ltd.

Inventor： Qiang LI ,  Jumei LI ,  Yinglai XI ,  Fei SU

IPC: H04N19/12 ,  H04N19/18 ,  H04N19/136

CPC classification number: H04N19/12 ,  H04N19/124 ,  H04N19/156 ,  H04N19/157 ,  H04N19/179 ,  H04N19/42 ,  H04N19/436

Abstract: A transform and inverse transform circuit is provided. The transform and inverse transform circuit includes: at least one quantization and inverse quantization circuit, including at least one quantization and inverse quantization unit, wherein each quantization and inverse quantization unit includes a plurality of first coefficients, and each quantization and inverse quantization unit performs quantization or inverse quantization on one of multiple ways of inputting data; and at least one one-dimensional transform circuit, coupled to the quantization and inverse quantization circuit, wherein the one-dimensional transform circuit includes a plurality of second coefficients, wherein the one-dimensional transform circuit performs one-dimensional transform on the inputting data processed by the quantization and inverse quantization circuit, wherein the plurality of first coefficients and the plurality of second coefficients are set up based on a video codec standard.

Abstract translation: 提供变换和逆变换电路。 变换和逆变换电路包括：至少一个量化和逆量化电路，包括至少一个量化和逆量化单元，其中每个量化和逆量化单元包括多个第一系数，并且每个量化和逆量化单元执行量化 或在多种输入数据方式之一上进行逆量化; 以及耦合到所述量化和逆量化电路的至少一个一维变换电路，其中所述一维变换电路包括多个第二系数，其中所述一维变换电路对所处理的输入数据执行一维变换 通过量化和逆量化电路，其中基于视频编解码器标准来建立多个第一系数和多个第二系数。

公开(公告)号：US20150341658A1

公开(公告)日：2015-11-26

申请号：US14818886

申请日：2015-08-05

Applicant: VIA Telecom Co., Ltd.

Inventor： Yinglai XI ,  Qiang LI ,  Jumei LI ,  Jianbin HE ,  Jinfeng ZHOU ,  Zhichong CHEN ,  Liu YANG ,  Dong LI

IPC: H04N19/547 ,  H04N19/122 ,  H04N19/82 ,  H04N19/117

CPC classification number: H04N19/547 ,  H04N19/117 ,  H04N19/122 ,  H04N19/433 ,  H04N19/50 ,  H04N19/523 ,  H04N19/533 ,  H04N19/56 ,  H04N19/82

Abstract: An in-loop filtering acceleration circuit applied in a video codec system supporting the H.264 standard and the VC-1 standard is provided. The circuit includes multiple one-dimensional (1D) filters configured to perform a filtering process; and a filter selection unit configured to select one of the 1D filters according to the value of the boundary strength to perform the filtering processing to the reconstructed macroblock. The in-loop filtering acceleration circuit further divides the reconstructed macroblock into multiple 8×8 blocks and multiple 4×4 blocks, performs the filtering process to horizontal edges of the 8×8 blocks the reconstructed macroblock row by row from bottom to top, and performs the filtering process to horizontal edges of the 4×4 blocks row by row from top to bottom.

Abstract translation: 提供了一种应用于支持H.264标准和VC-1标准的视频编解码器系统中的环路滤波加速电路。 该电路包括被配置为执行滤波处理的多个一维（1D）滤波器; 以及滤波器选择单元，被配置为根据边界强度的值来选择一个1D滤波器，以对重建的宏块执行滤波处理。 环路滤波加速电路进一步将重建的宏块划分为多个8×8块和多个4×4块，对重建的宏块逐个从底部到顶部的8×8块的水平边缘进行滤波处理， 从上到下逐行执行4×4块的水平边缘的过滤处理。