公开(公告)号：US20150006755A1

公开(公告)日：2015-01-01

申请号：US13927160

申请日：2013-06-26

Applicant: Verizon Patent and Licensing Inc.

Inventor： Matthew W. Turlington ,  Michael U. Bencheck

IPC: H04L12/813

CPC classification number: H04L47/20 ,  H04L41/0893 ,  H04L41/5019 ,  H04L47/326 ,  H04L47/41 ,  H04L47/527 ,  Y02B70/30 ,  Y02D50/30

Abstract: A master network interface device (NID) receives a first packet flow associated with a particular customer via a first link of a link aggregation group (LAG). The master NID also receives, from a non-master NID, an indication of a second packet flow, associated with the particular customer, that are traversing a second link of the LAG. The master NID applies collective rate limiting criteria to the first packet flow and to the second packet flow, such that the collective rate limiting criteria enforces a SLA rate for the particular customer. The master NID forwards at least some of the first packet flow via the first link, based on the rate limiting criteria as applied to the first packet flow. The master NID also sends, to the non-master network interface device, an indication of the rate limiting criteria as applied to the second packet flow.

Abstract translation: 主网络接口设备（NID）经由链路聚合组（LAG）的第一链路接收与特定客户相关联的第一分组流。 主NID还从非主NID接收与特定客户相关联的正在遍历LAG的第二链路的第二分组流的指示。 主NID将集合速率限制标准应用于第一分组流和第二分组流，使得集合速率限制标准对特定客户实施SLA速率。 基于应用于第一分组流的速率限制标准，主NID经由第一链路转发至少一些第一分组流。 主NID还向非主网络接口设备发送应用于第二分组流的速率限制标准的指示。

公开(公告)号：US20130294769A1

公开(公告)日：2013-11-07

申请号：US13933199

申请日：2013-07-02

Applicant: Verizon Patent and Licensing Inc.

Inventor： Scott R. Kotrla ,  Matthew W. Turlington ,  Michael U. Bencheck ,  Tiejun J. Xia

IPC: H04B10/077

CPC classification number: H04B10/0775 ,  H04B2210/078

Abstract: A bit error generating device includes a light source, an input device, and a control processor. The control processor includes logic configured to: receive protocol or bitrate information regarding a live traffic signal via the input device; determine bit error simulation signal parameters based on the received protocol or bitrate information; configure the light source to generate the bit error simulation signal based on the bit error simulation signal parameters; and instruct the light source to inject the bit error simulation signal into an optical fiber carrying the live traffic signal.

Abstract translation: 位错误产生装置包括光源，输入装置和控制处理器。 所述控制处理器包括被配置为：经由所述输入设备接收关于实况交通信号的协议或比特率信息的逻辑; 基于接收的协议或比特率信息确定误码仿真信号参数; 根据误码仿真信号参数配置光源产生误码仿真信号; 并指示光源将位错误模拟信号注入到携带实时话务信号的光纤中。

公开(公告)号：US09948497B2

公开(公告)日：2018-04-17

申请号：US13836704

申请日：2013-03-15

Applicant: Verizon Patent and Licensing Inc.

Inventor： Michael U. Bencheck ,  Matthew W. Turlington ,  Vincent A. Alesi ,  Richard Schell ,  William F. Copeland

IPC: H04L12/24

CPC classification number: H04L41/0213 ,  H04L41/0809

Abstract: A system for and method of automatic discovery and configuration of network interface devices is presented. A network interface device (NID) may be included a pre-configured maintenance entity end point (MEP), whereby upon use, the NID may begin sending at least one discovery message to a provider edge device, each discovery message including an organizationally unique identifier. The provider edge device may strip the discovery message(s) to determine the message content, which may then be forwarded to a NIS management system. The NID management system may then identify an identification number of the NID, determine where the NID is installed and send any configuration data to the NID via the provider edge device to configure the NID.

公开(公告)号：US09882817B2

公开(公告)日：2018-01-30

申请号：US13927160

申请日：2013-06-26

Applicant: Verizon Patent and Licensing Inc.

Inventor： Matthew W. Turlington ,  Michael U. Bencheck

IPC: G06F15/16 ,  H04L12/813 ,  H04L12/823 ,  H04L12/891 ,  H04L12/873 ,  H04L12/24

CPC classification number: H04L47/20 ,  H04L41/0893 ,  H04L41/5019 ,  H04L47/326 ,  H04L47/41 ,  H04L47/527 ,  Y02B70/30 ,  Y02D50/30

Abstract: A master network interface device (NID) receives a first packet flow associated with a particular customer via a first link of a link aggregation group (LAG). The master NID also receives, from a non-master NID, an indication of a second packet flow, associated with the particular customer, that are traversing a second link of the LAG. The master NID applies collective rate limiting criteria to the first packet flow and to the second packet flow, such that the collective rate limiting criteria enforces a SLA rate for the particular customer. The master NID forwards at least some of the first packet flow via the first link, based on the rate limiting criteria as applied to the first packet flow. The master NID also sends, to the non-master network interface device, an indication of the rate limiting criteria as applied to the second packet flow.

公开(公告)号：US08873949B2

公开(公告)日：2014-10-28

申请号：US13933199

申请日：2013-07-02

Applicant: Verizon Patent and Licensing Inc.

Inventor： Scott R. Kotrla ,  Matthew W. Turlington ,  Michael U. Bencheck ,  Tiejun J. Xia

IPC: H04B10/00

CPC classification number: H04B10/0775 ,  H04B2210/078

Abstract: A bit error generating device includes a light source, an input device, and a control processor. The control processor includes logic configured to: receive protocol or bitrate information regarding a live traffic signal via the input device; determine bit error simulation signal parameters based on the received protocol or bitrate information; configure the light source to generate the bit error simulation signal based on the bit error simulation signal parameters; and instruct the light source to inject the bit error simulation signal into an optical fiber carrying the live traffic signal.

Abstract translation: 位错误产生装置包括光源，输入装置和控制处理器。 所述控制处理器包括被配置为：经由所述输入设备接收关于实况交通信号的协议或比特率信息的逻辑; 基于接收的协议或比特率信息确定位错误模拟信号参数; 根据误码仿真信号参数配置光源产生误码仿真信号; 并指示光源将位错误模拟信号注入到携带实时话务信号的光纤中。