公开(公告)号：US20060031705A1

公开(公告)日：2006-02-09

申请号：US11246427

申请日：2005-10-07

申请人： Victor Augsburg ,  James Dieffenderfer ,  Bernard Drerup ,  Richard Hofmann ,  Thomas Sertorius ,  Barry Wolford

发明人： Victor Augsburg ,  James Dieffenderfer ,  Bernard Drerup ,  Richard Hofmann ,  Thomas Sertorius ,  Barry Wolford

IPC分类号： G06F5/06

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

公开(公告)号：US20050055655A1

公开(公告)日：2005-03-10

申请号：US10971947

申请日：2004-10-22

申请人： Victor Augsburg ,  James Dieffenderfer ,  Bernard Drerup ,  Richard Hofmann ,  Thomas Sartorius ,  Barry Wolford

发明人： Victor Augsburg ,  James Dieffenderfer ,  Bernard Drerup ,  Richard Hofmann ,  Thomas Sartorius ,  Barry Wolford

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.

摘要翻译： 一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。 芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。 相对于默认传播时间确定信号从源设备传播到目的地设备的时间。 然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。 每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。 使用附加逻辑，当管道级插入各种路径时，不需要更改设备。 寄存器被用作插入到路径内的流水线级。

公开(公告)号：US20080109610A1

公开(公告)日：2008-05-08

申请号：US11970599

申请日：2008-01-08

申请人： James Dieffenderfer ,  Bernard Drerup ,  Jaya Ganasan ,  Richard Hofmann ,  Thomas Sartorius ,  Thomas Speier ,  Barry Wolford

发明人： James Dieffenderfer ,  Bernard Drerup ,  Jaya Ganasan ,  Richard Hofmann ,  Thomas Sartorius ,  Thomas Speier ,  Barry Wolford

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  Y02D10/13

摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

摘要翻译： 一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据 主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。 只有那些可能具有请求的数据的非始发侦听主机才被查询。 所有被查询的非始发侦听主人都回复。 如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。 如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

公开(公告)号：US20060174068A1

公开(公告)日：2006-08-03

申请号：US11050295

申请日：2005-02-03

申请人： Bernard Drerup ,  Richard Nicholas ,  Barry Wolford

发明人： Bernard Drerup ,  Richard Nicholas ,  Barry Wolford

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

公开(公告)号：US20080071954A1

公开(公告)日：2008-03-20

申请号：US11944644

申请日：2007-11-26

申请人： Bernard Drerup ,  Richard Nicholas ,  Barry Wolford

发明人： Bernard Drerup ,  Richard Nicholas ,  Barry Wolford

IPC分类号： G06F13/18

CPC分类号： G06F13/28

摘要： A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

摘要翻译： 提供了一种方法和总线预取机制，用于实现增强的缓冲区控制。 计算机系统包括多个主器件和至少一个从器件通过系统总线交换数据，并且从器件在主器件的控制下预读取数据。 主机产生指示新的或持续请求的继续总线信号。 主机产生一个预取总线信号，指示预取量，包括不预取。 主机包括用于继续读取序列的机制，允许预取，直到作出指示预取量为零的请求。

公开(公告)号：US20060020778A1

公开(公告)日：2006-01-26

申请号：US10897345

申请日：2004-07-22

申请人： Jimmie Edrington ,  Barry Wolford

发明人： Jimmie Edrington ,  Barry Wolford

IPC分类号： G06F15/177

CPC分类号： G06F13/1694

摘要： The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module and a memory device and is configured to receive initialization control commands and associated configuration information from the configuration module, and to send memory initialization commands to the memory device based on received initialization control commands and associated configuration information.

摘要翻译： 本发明提供了一种用于可编程存储器初始化的系统。 配置模块配置有初始化控制命令和相关配置信息。 初始化模块耦合到配置模块和存储器设备，并被配置为从配置模块接收初始化控制命令和相关联的配置信息，并且基于接收的初始化控制命令和相关联的配置信息向存储器设备发送存储器初始化命令 。

公开(公告)号：US20070047378A1

公开(公告)日：2007-03-01

申请号：US11553588

申请日：2006-10-27

申请人： Barry Wolford ,  James Sullivan

发明人： Barry Wolford ,  James Sullivan

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/04 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/0411 ,  G11C2211/4061

摘要： In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with write operations. Correspondingly, the memory controller configures its write data mask output as a status input at such times, for receipt of status signaling from the memory module. In one embodiment, the memory module maintains a status register related to one or more operating conditions of the module, such as temperature, and signals status information changes to the memory controller by driving the module's data mask input. In response to such signaling, the memory controller initiates a read of the module's status register to obtain updated status information, and takes appropriate action, such as by changing the module's refresh rate.

摘要翻译： 在本文教导的一个实施例中，存储器模块选择性地使用其写入数据掩模输入作为其向其提供状态信号给相关联的存储器控​​制器的状态输出。 存储器模块将其数据掩码输入配置为一次或多次的状态输出，而不与写入操作冲突。 相应地，存储器控制器将其写入数据掩模输出配置为在这种时间的状态输入，以从存储器模块接收状态信号。 在一个实施例中，存储器模块通过驱动模块的数据掩码输入来维持与模块的一个或多个操作条件相关的状态寄存器，例如温度，以及信号状态信息改变到存储器控制器。 响应于这种信令，存储器控制器启动对模块的状态寄存器的读取以获得更新的状态信息，并且采取适当的动作，例如通过改变模块的刷新率。

公开(公告)号：US07210030B2

公开(公告)日：2007-04-24

申请号：US10897345

申请日：2004-07-22

申请人： Jimmie D. Edrington ,  Barry Wolford

发明人： Jimmie D. Edrington ,  Barry Wolford

IPC分类号： G06F9/445 ,  G06F15/177

CPC分类号： G06F13/1694

摘要： The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module and a memory device and is configured to receive initialization control commands and associated configuration information from the configuration module, and to send memory initialization commands to the memory device based on received initialization control commands and associated configuration information.

摘要翻译： 本发明提供了一种用于可编程存储器初始化的系统。 配置模块配置有初始化控制命令和相关配置信息。 初始化模块耦合到配置模块和存储器设备，并被配置为从配置模块接收初始化控制命令和相关联的配置信息，并且基于接收的初始化控制命令和相关联的配置信息向存储器设备发送存储器初始化命令 。