公开(公告)号：US20080098134A1

公开(公告)日：2008-04-24

申请号：US11574513

申请日：2005-08-31

申请人： Victor Martinus Van Acht ,  Martinus Wilhelmus Blum ,  Nicolas Lambert ,  Pierre Hermanus Woerlee

发明人： Victor Martinus Van Acht ,  Martinus Wilhelmus Blum ,  Nicolas Lambert ,  Pierre Hermanus Woerlee

IPC分类号： G06F13/18

CPC分类号： G06F21/78 ,  G06F21/35

摘要： A portable storage device (MC) is disclosed, which comprises a memory (MEM) for storing data (DAT), a data interface (INT) for exchanging data (DAT) between the memory (MEM) and a host device (DEV), radio communication interface (RI) designed for receiving a key (K) from a transponder (T), checking means (COMP) for checking if a key (K) has a predefined value (V, and access inhibit means (SW) for controlling access to the memory (MEM), wherein the access inhibit means (SW) are controlled by the checking means (COMP). Access to the memory (MEM) is only granted if a certain key (K) can be received, which means that a certain transponder (T) has to be in the vicinity of the portable storage device (MC) for granting access. Furthermore, data (DAT) which is transferred from host device (DEV) to memory (MEM) can be encrypted and data (DAT) which is transferred from memory (MEM) to host device (DEV) can be decrypted. In this way for example commonly used memory cards can be secured against unauthorized use.

摘要翻译： 公开了一种便携式存储设备（MC），其包括用于存储数据（DAT）的存储器（MEM），用于在存储器（MEM）和主机设备（DEV）之间交换数据（DAT）的数据接口（INT） 无线电通信接口（RI），用于从应答器（T）接收密钥（K）;检查装置（COMP），用于检查密钥（K）是否具有预定义的值（V，以及用于控制的接入禁止装置 访问存储器（MEM），其中访问禁止装置（SW）由检查装置（COMP）控制。仅当可以接收到某个密钥（K）时才允许访问存储器（MEM），这意味着 某个应答器（T）必须位于便携式存储设备（MC）附近，用于授权访问，此外，可以对从主机设备（DEV）传送到存储器（MEM）的数据（DAT）进行加密和数据（ 从存储器（MEM）传送到主机设备（DEV）的DAT）可以被解密，例如可以固定普通的存储卡 授权使用。

公开(公告)号：US08081523B2

公开(公告)日：2011-12-20

申请号：US11813862

申请日：2006-01-05

申请人： Victor Martinus Van Acht ,  Nicolaas Lambert ,  Pierre Hermanus Woerlee

发明人： Victor Martinus Van Acht ,  Nicolaas Lambert ,  Pierre Hermanus Woerlee

IPC分类号： G11C5/14

CPC分类号： G11C7/14

摘要： A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.

摘要翻译： 电路包括存储器单元阵列（10）。 多个感测电路（20）耦合到相应存储单元（10）的输出（14），用于将存储单元（10）中的相应一个的输出信号与参考信号进行比较以形成数据信号 来自存储单元（10）中的相应一个的输出信号。 参考发生器电路（24,26）从一个和形成参考信号，其中寻址组的每个存储单元（10）中的每个相应的一个贡献作为存储单元的相应一个的输出信号的函数 （10）。 在超过参考信号的饱和距离上的输出信号值的贡献相等，并且在超过参考信号以下的饱和距离处的输出信号值的贡献相等。 在单元格中存储多级数据的情况下，从基准电平以上和低于基准电平的中心电平到饱和电平的距离是相互不同的，其比率对应于已经被编程的单元计数的比率 各级别。

公开(公告)号：US07580275B2

公开(公告)日：2009-08-25

申请号：US11817754

申请日：2006-03-03

申请人： Teunis Jan Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

发明人： Teunis Jan Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

摘要翻译： 使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。 在第二个 在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到 在执行全部列更新命令期间的第二空闲状态（12）。 控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II） 分别。

公开(公告)号：US07643327B2

公开(公告)日：2010-01-05

申请号：US11817715

申请日：2006-02-28

申请人： Teunis Jian Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

发明人： Teunis Jian Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

IPC分类号： G11C11/56

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/0028 ,  G11C2213/15 ,  G11C2213/72

摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.

摘要翻译： 存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。 电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。 在所选行中的列端子和单元（20）的行端子之间施加电压差，以便执行读取动作。 这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。 电压差被施加在所选列的单元（20）的列端子和行端子之间，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。 擦除动作的电压差具有读极性。 此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。 写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

公开(公告)号：US20090129190A1

公开(公告)日：2009-05-21

申请号：US11817715

申请日：2006-02-28

申请人： Teunis Jian Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

发明人： Teunis Jian Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

IPC分类号： G11C7/00 ,  G11C11/416 ,  G11C8/00 ,  G11C5/14

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/0028 ,  G11C2213/15 ,  G11C2213/72

摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.

摘要翻译： 存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。 电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。 在所选行中的列端子和单元（20）的行端子之间施加电压差，以便执行读取动作。 这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。 电压差被施加在所选列的单元（20）的列端子和行端子之间，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。 擦除动作的电压差具有读极性。 此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。 写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

公开(公告)号：US20090122590A1

公开(公告)日：2009-05-14

申请号：US11817754

申请日：2006-03-03

申请人： Teunis Jan Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

发明人： Teunis Jan Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

摘要翻译： 使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。 在第二个 在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到 在执行全部列更新命令期间的第二空闲状态（12）。 控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II） 分别。

公开(公告)号：US20060184923A1

公开(公告)日：2006-08-17

申请号：US10562888

申请日：2004-06-30

申请人： Orlando Pires Dos Reis Moreira ,  Victor Martinus Van Acht ,  Bernardo De Oliveira Kstrup Pereira

发明人： Orlando Pires Dos Reis Moreira ,  Victor Martinus Van Acht ,  Bernardo De Oliveira Kstrup Pereira

IPC分类号： G06F9/45

CPC分类号： G06F9/5061 ,  G06F2209/505

摘要： A processor system is described comprising at least a first and a second processor element (PEI, PE2). The first processor element (PEI) has a cluster request indicator (CR12) related to the second processor element and the second processor element (PE2) has a cluster request indicator (CR21) related to the first processor element. The processor elements have an instruction set enabling dynamic control of the indicators. The indicators (CR12, CR21) have a value range comprising at least a first value (positive indicator) indicating that the processor element requests to form a cluster with the related processor element, and a second value (negative indicator) indicating that the processor element does not request to form a cluster with the related processor element. The system further comprises a cluster control facility (CC12) which detects the value of the cluster request indicator and organizes the processor elements in clusters in accordance with the detected values. Two processor elements belong to the same cluster if they have positive indicators related to each other, or if there is a sequence of processor elements comprising those two processor elements wherein each pair of subsequent processor elements has positive indicators related to each other.

摘要翻译： 描述了包括至少第一和第二处理器元件（PEI，PE 2）的处理器系统。 第一处理器元件（PEI）具有与第二处理器元件相关的簇请求指示符（CR12），第二处理器元件（PE2）具有与第一处理器元件相关的簇请求指示符（CR 21）。 处理器元件具有使指示器能够动态控制的指令集。 指示符（CR 12，CR 21）具有包括至少指示处理器元件请求与相关处理器元件形成簇的至少第一值（正指示符）的值范围，以及指示第 处理器元件不要求与相关处理器元件形成集群。 该系统还包括一个集群控制设备（CC12），该集群控制设备（CC12）根据检测到的值检测集群请求指示符的值并将处理器元件组织在一起。 如果两个处理器元件具有彼此相关的正指示器，或者如果存在包括这两个处理器元件的处理器元件序列，则其中每对后续处理器元件具有彼此相关的正指示器，那么两个处理器元件属于相同的簇。

公开(公告)号：US20080208518A1

公开(公告)日：2008-08-28

申请号：US11914653

申请日：2006-05-09

申请人： Hans Marc Boeve ,  Teunis Jan Ikkink ,  Victor Martinus Van Acht

发明人： Hans Marc Boeve ,  Teunis Jan Ikkink ,  Victor Martinus Van Acht

IPC分类号： G06F15/00

CPC分类号： G01C17/30

摘要： Systems (1) comprising generating devices (2) comprising sensors (21) for generating sensor signals representing orientations of the generating devices (2) are provided with comparing devices (3) comprising comparators (31) for comparing the sensor signals with reference signals for interpreting the orientations, to increase the number of possible applications. The generating devices (2) and the comparing devices (3) may form parts of one apparatus (4) or of different apparatuses and then communicate wiredly or wirelessly via radio or infrared. Reference sensors (33,52) for generating the reference signals and/or reference memories (34,53) for storing the reference signals may be located in the comparing devices (3) and/or in sources (5) and then communicate wiredly or wirelessly via radio or infrared. Further comparators (36) in the comparing devices (3) may introduce adjustable sensitivities.

摘要翻译： 包括产生装置（2）的系统（1）包括用于产生表示生成装置（2）的取向的传感器信号的传感器（21），比较装置（3）包括比较器（31），用于将传感器信号与参考信号进行比较 解释方向，增加可能应用的数量。 生成装置（2）和比较装置（3）可以形成一个装置（4）或不同装置的部分，然后通过无线电或红外线有线或无线地进行通信。 用于产生参考信号的参考传感器（33,52）和/或用于存储参考信号的参考存储器（34,53）可以位于比较装置（3）和/或源（5）中，然后有线或 通过无线电或红外无线方式。 比较装置（3）中的其它比较器（36）可以引入可调节的灵敏度。