CHAINED BUS METHOD AND DEVICE
    1.
    发明申请
    CHAINED BUS METHOD AND DEVICE 有权
    链接总线方法和设备

    公开(公告)号:US20100042750A1

    公开(公告)日:2010-02-18

    申请号:US12192450

    申请日:2008-08-15

    IPC分类号: G06F13/14

    摘要: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

    摘要翻译: 描述和示出了能够在链中配置的存储器件和方法。 在一个配置中,主机使用单个数据输入端口和单个数据输出端口与存储器设备链路进行通信。 描述了将标识符分配给链中的存储器件的方法,其包括检测下游存储器件的存在或不存在。 在所选择的示例中,标识符被顺序分配给链中的存储设备,直到没有检测到附加的下游存储器设备。

    Chained bus method and device
    2.
    发明授权
    Chained bus method and device 有权
    链式总线方法和装置

    公开(公告)号:US08560735B2

    公开(公告)日:2013-10-15

    申请号:US12192450

    申请日:2008-08-15

    IPC分类号: G06F3/00

    摘要: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

    摘要翻译: 描述和示出了能够在链中配置的存储器件和方法。 在一个配置中,主机使用单个数据输入端口和单个数据输出端口与存储器设备链路进行通信。 描述了将标识符分配给链中的存储器件的方法,其包括检测下游存储器件的存在或不存在。 在所选择的示例中,标识符被顺序地分配给链中的存储设备,直到没有检测到附加的下游存储器设备。